[PATCH RFC 07/11] arm64: dts: qcom: sm6350: Affirm IDR0.CCTW on apps_smmu

From: Konrad Dybcio
Date: Wed Sep 18 2024 - 18:59:27 EST


From: Konrad Dybcio <quic_kdybcio@xxxxxxxxxxx>

On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent
pagetable walk via the IDR0 register. This however is not respected by
the arm-smmu driver unless dma-coherent is set.

Mark the node as dma-coherent to ensure this (and other) implementations
take this coherency into account.

Signed-off-by: Konrad Dybcio <quic_kdybcio@xxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/sm6350.dtsi | 1 +
1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index 7986ddb30f6e8ce6ceeb0f90772b0243aed6bffe..54cfe99006613f8ccc5bf6d83bcb4bf8e72f3cfe 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -2685,6 +2685,7 @@ apps_smmu: iommu@15000000 {
<GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
};

intc: interrupt-controller@17a00000 {

--
2.46.1