On Wed, Sep 25, 2024 at 11:46:35AM +0200, Konrad Dybcio wrote:Sorry, I misunderstood what you mean. I only verified if link was up but ignored the status of ep device
On 25.09.2024 11:30 AM, Konrad Dybcio wrote:Yeah, that's for using GIC-ITS to receive MSIs. But the default one is the
On 25.09.2024 10:05 AM, Manivannan Sadhasivam wrote:
On Tue, Sep 24, 2024 at 04:26:34PM +0200, Konrad Dybcio wrote:You would think so :P
On 24.09.2024 12:14 PM, Qiang Yu wrote:Is it based on x1e80100?
Describe PCIe3 controller and PHY. Also add required system resources likeQiang, Mani
regulators, clocks, interrupts and registers configuration for PCIe3.
Signed-off-by: Qiang Yu <quic_qianyu@xxxxxxxxxxx>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
---
I have a RTS5261 mmc chip on PCIe3 on the Surface Laptop.
There's no msi-map for PCIe3. I recall +Johan talking about some sort ofAdding the global irq breaks sdcard detection (the chip still comesYeah, I did see some issues with MSI on SM8250 (RB5) when global interrupts are
up fine) somehow. Removing the irq makes it work again :|
I've confirmed that the irq number is correct
enabled and I'm working with the hw folks to understand what is going on. But
I didn't see the same issues on newer platforms (sa8775p etc...).
Can you please confirm if the issue is due to MSI not being received from the
device? Checking the /proc/interrutps is enough.
a bug that prevents us from adding it?
internal MSI controller in DWC.
Unless you just meant the msi0..=7 interrupts, then yeah, I only get one irqOk. Then most likely the same issue I saw on SM8250 as well. But I'm confused
event with "global" in place and it seems to never get more
why Qiang didn't see the issue. I specifically asked him to add the global
interrupt and test it with the endpoint to check if the issue arises or not.
Qiang, can you please confirm?
- Mani