Re: [PATCH v4 1/6] i2c: npcm: correct the read/write operation procedure

[Tyrone Ting]

Hi Andi:

Thank you for your help.

Andi Shyti <andi.shyti@xxxxxxxxxx> 於 2024年9月26日 週四 上午4:19寫道：
>
> Hi Tyrone,
>
> On Fri, Sep 20, 2024 at 06:18:15PM GMT, warp5tw@xxxxxxxxx wrote:
> > From: Tyrone Ting <kfting@xxxxxxxxxxx>
> >
> > From: Tyrone Ting <kfting@xxxxxxxxxxx>
>
> no worries, I can take care of this.
>
> > Originally the driver uses the XMIT bit in SMBnST register to decide
> > the upcoming i2c transaction. If XMIT bit is 1, then it will be an i2c
> > write operation. If it's 0, then a read operation will be executed.
> >
> > In slave mode the XMIT bit can simply be used directly to set the state.
> > XMIT bit can be used as an indication to the current state of the state
> > machine during slave operation. (meaning XMIT = 1 during writing and
> > XMIT = 0 during reading).
> >
> > In master operation XMIT is valid only if there are no bus errors.
> > For example: in a multi master where the same module is switching from
> > master to slave at runtime, and there are collisions, the XMIT bit
> > cannot be trusted.
> >
> > However the maser already "knows" what the bus state is, so this bit
> > is not needed and the driver can just track what it is currently doing.
> >
> > Signed-off-by: Tyrone Ting <kfting@xxxxxxxxxxx>
> > Reviewed-by: Tali Perry <tali.perry1@xxxxxxxxx>
>
> This patch is independent from the rest of the series, can I
> start takin this in and unburden you from this?
>

Sure, thank you again.

> Andi

Regards,
Tyrone