Re: [PATCH 2/2] dt-bindings: mmc: mtk-sd: Add support for MT8196

[Andy-ld Lu (卢东)]

On Sat, 2024-09-28 at 15:39 +0200, Krzysztof Kozlowski wrote:
>  	 
> External email : Please do not click links or open attachments until
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>  On 28/09/2024 15:14, Andy-ld Lu (卢东) wrote:
> > On Thu, 2024-09-26 at 12:54 -0500, Rob Herring wrote:
> >>   
> >> External email : Please do not click links or open attachments
> until
> >> you have verified the sender or the content.
> >>  On Thu, Sep 26, 2024 at 03:03:18PM +0800, Andy-ld Lu wrote:
> >>> Extend the devicetree bindings to include the MT8196 mmc
> controller
> >>> by adding the compatible string 'mediatek,msdc-v2', which could
> be
> >>> also used for future compatible SoCs that support new tx/rx.
> >>
> >> Generally, every SoC ends up changing at least slightly. So we
> don't
> >> do 
> >> version numbers except when there's a well defined versioning
> scheme
> >> of 
> >> the h/w (e.g. FPGA IP blocks). So, use SoC for compatible string.
> > Thanks for your review.
> > 
> > The new tx/rx represents a significant update for mmc controller of
> > mediatek from the MT8196 chipset, and the dependent settings remain
> > consistent for MT8196 and subsequent SoCs. Therefore, It is
> proposed to
> > use a unified compatible string for these SoCs that support new
> tx/rx,
> > and name it as 'IP(msdc) version two'.
> 
> Sorry, nope. That's not valid reasons.

Thanks for your review.

I will follow your comment in next change.

> 
> >>
> >>>
> >>> Add three properties for MT8196 settings:
> >>> - 'mediatek,prohibit-gate-cg', indicate if the source clock CG
> >> could
> >>>   be disabled when CPU access IP registers.
> >>>
> >>> - 'mediatek,stop-dly-sel', configure read data clock stops at
> block
> >> gap.
> >>>
> >>> - 'mediatek,pop-en-cnt', configure the margins of write and read
> >>>   pointers while begin to pop data transfer.
> >>>
> >>> Signed-off-by: Andy-ld Lu <andy-ld.lu@xxxxxxxxxxxx>
> >>> ---
> >>>  .../devicetree/bindings/mmc/mtk-sd.yaml       | 26
> >> +++++++++++++++++++
> >>>  1 file changed, 26 insertions(+)
> >>>
> >>> diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> >> b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> >>> index c532ec92d2d9..82d1a9fac67c 100644
> >>> --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> >>> +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> >>> @@ -25,6 +25,7 @@ properties:
> >>>            - mediatek,mt8173-mmc
> >>>            - mediatek,mt8183-mmc
> >>>            - mediatek,mt8516-mmc
> >>> +          - mediatek,msdc-v2
> >>>        - items:
> >>>            - const: mediatek,mt7623-mmc
> >>>            - const: mediatek,mt2701-mmc
> >>> @@ -154,6 +155,30 @@ properties:
> >>>      enum: [32, 64]
> >>>      default: 32
> >>>  
> >>> +  mediatek,stop-dly-sel:
> >>> +    $ref: /schemas/types.yaml#/definitions/uint32
> >>> +    description:
> >>> +      Some SoCs need to set appropriate stop-dly-sel to
> configure
> >> read data clock
> >>> +      stops at block gap. The valid range is from 0 to 0xf.
> >>
> >> SoC dependent or board dependent? Imply from the compatible for
> the 
> >> former. A property is fine for the latter case.
> > Yes, it is SoC dependent in principle, but we would like to use a
> > unified compatible string for MT8196 and subsequent SoCs as
> mentioned
> 
> Also no :(. Use SoC specific compatible.

I will follow your comment in next change.

> 
> > above, and this register setting(not relavant with new tx/rx) may
> be
> > variant. Therefore, want to use the property of device tree to set
> > individually.
> >>
> >>> +    minimum: 0
> >>> +    maximum: 0xf
> >>> +
> >>> +  mediatek,pop-en-cnt:
> >>> +    $ref: /schemas/types.yaml#/definitions/uint32
> >>> +    description:
> >>> +      Some SoCs need to set appropriate pop-en-cnt to configure
> >> the margins of write
> >>> +      and read pointers while begin to pop data transfer. The
> >> valid range is from 0
> >>> +      to 0xf.
> >>> +    minimum: 0
> >>> +    maximum: 0xf
> >>
> >> Same question.
> > Same as the reply above.
> >>
> >>> +
> >>> +  mediatek,prohibit-gate-cg:
> >>> +    $ref: /schemas/types.yaml#/definitions/flag
> >>> +    description:
> >>> +      Decide if source clock CG could be disabled when CPU
> access
> >> IP registers.
> >>> +      If present, source clock CG could not be disabled.
> >>> +      If not present, source clock CG could be disabled.
> >>
> >>
> >> Sounds like you need to describe the clock in "clocks".
> > It is not with clock itself, but rather with the bus design that
> would
> > check the 'source_cg' status bit to decide whether to prevent the
> CPU
> > from accessing the IP registers. And there have been no changes to
> the
> > 'source_cg'(already been descirbed before) for MT8196.
> 
> I don't understand why do you need this property if it was already
> described. Please do not describe things twice.

I will follow your comment in next change.

> 
> 
> Best regards,
> Krzysztof
>