[PATCH 0/2] ti-cpufreq: AM62: Backward compatibility for syscon and update offsets

[Dhruva Gole]

With the Silicon revision being taken directly from socinfo, there's no
longer any need for reading any SOC register for revision from this driver.
Hence, we do not require any rev_offset for AM62 family of devices.

Also, maintain the backward compatibility with old devicetree, and hence
add condition to handle the case where we have the zero offset such that we
don't end up reading the wrong register offset in new AM625 DTs whenever we fix
them up.

These patches have been in discussion as part of another series, which is now
being split up as per discussions with Nishanth. Ref. the following link for
more context on the same:
https://lore.kernel.org/all/20240926-ti-cpufreq-fixes-v5-v7-0-3c94c398fe8f@xxxxxx/

**DEPENDS ON:**
"mfd: syscon: Use regmap max_register_is_0 as needed"
https://lore.kernel.org/linux-arm-kernel/20240903184710.1552067-1-nm@xxxxxx/

This series has been tested on AM625 on top of above patch:
https://gist.github.com/DhruvaG2000/40b80cc04a9ac90c86445d6e67ece4cb

Signed-off-by: Dhruva Gole <d-gole@xxxxxx>
---
Dhruva Gole (2):
      cpufreq: ti-cpufreq: Allow backward compatibility for efuse syscon
      cpufreq: ti-cpufreq: Remove revision offsets in AM62 family

 drivers/cpufreq/ti-cpufreq.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)
---
base-commit: cea5425829f77e476b03702426f6b3701299b925
change-id: 20240930-b4-ti-cpufreq-am62-quirk-46242e3daa2b

Best regards,
-- 
Dhruva Gole <d-gole@xxxxxx>