Re: [PATCH v3 2/2] i2c: dwsignware: determine HS tHIGH and tLOW based on HW parameters

[Andi Shyti]

Hi Michael,

On Tue, Oct 01, 2024 at 04:29:34PM GMT, Michael Wu wrote:
> In commit 35eba185fd1a ("i2c: designware: Calculate SCL timing parameter
> for High Speed Mode") hs_hcnt and hs_lcnt are calculated based on fixed
> tHIGH = 160 and tLOW = 120. However, the set of these fixed values only
> applies to the combination of hardware parameters IC_CAP_LOADING = 400pF
> and IC_CLK_FREQ_OPTIMIZATION = 1. Outside of this combination, if these
> fixed tHIGH = 160 and tLOW = 120 are still used, the calculated hs_hcnt
> and hs_lcnt may not be small enough, making it impossible for the SCL
> frequency to reach 3.4 MHz.

If someone is not familiar with the terms you are using this
paragraph is completely meaningless. Can you please describe or
at least expandi in parenthesis:

  hs_hcnt
  hs_lcnt
  tHIGH/tLOW (this is easy, but redundancy in commit log is never
              enough)
  IC_CAP_LOADING
  IC_CLK_FREQ_OPTIMIZATION

> Section 3.15.4.5 in DesignWare DW_apb_i2b Databook v2.03 says that when
> IC_CLK_FREQ_OPTIMIZATION = 0,
> 
>     MIN_SCL_HIGHtime = 60 ns for 3.4 Mbps, bus loading = 100pF
> 		     = 120 ns for 3.4 Mbps, bus loading = 400pF
>     MIN_SCL_LOWtime = 160 ns for 3.4 Mbps, bus loading = 100pF
> 		    = 320 ns for 3.4 Mbps, bus loading = 400pF
> 
> and section 3.15.4.6 says that when IC_CLK_FREQ_OPTIMIZATION = 1,
> 
>     MIN_SCL_HIGHtime = 60 ns for 3.4 Mbps, bus loading = 100pF
> 		     = 160 ns for 3.4 Mbps, bus loading = 400pF
>     MIN_SCL_LOWtime = 120 ns for 3.4 Mbps, bus loading = 100pF
> 		    = 320 ns for 3.4 Mbps, bus loading = 400pF
> 
> In order to calculate more accurate hs_hcnt amd hs_lcnt, two hardware
> parameters IC_CAP_LOADING and IC_CLK_FREQ_OPTIMIZATION must be
> considered together.
> 
> Signed-off-by: Michael Wu <michael.wu@xxxxxxxxx>
> ---

...

> + * @bus_capacitance_pf: bus capacitance in picofarads
> + * @clk_freq_optimized: indicate whether hardware input clock frequency is

/indicate/indicates/
/hardware/the hardware/

> + *	reduced by reducing the internal latency

The sentence above is not really meaningful and it's not
describing what "clk_freq_optimized" is.

>   *
>   * HCNT and LCNT parameters can be used if the platform knows more accurate
>   * values than the one computed based only on the input clock frequency.

...

> +			u32 t_high, t_low;
> +
> +			/*
> +			 * The legal values stated in the databook for bus
> +			 * capacitance are only 100pF and 400pF.
> +			 * If dev->bus_capacitance_pf is greater than or equals
> +			 * to 400, t_high and t_low are assumed to be
> +			 * appropriate values for 400pF, otherwise 100pF.
> +			 */
> +			if (dev->bus_capacitance_pf >= 400) {
> +				/* assume bus capacitance is 400pF */
> +				t_high = dev->clk_freq_optimized ? 160 : 120;
> +				t_low = 320;
> +			} else {
> +				/* assume bus capacitance is 100pF */
> +				t_high = 60;
> +				t_low = dev->clk_freq_optimized ? 120 : 160;
> +			}
> +
>  			ic_clk = i2c_dw_clk_rate(dev);
>  			dev->hs_hcnt =
>  				i2c_dw_scl_hcnt(dev,
>  						DW_IC_HS_SCL_HCNT,
>  						ic_clk,
> -						160,	/* tHIGH = 160 ns */
> +						t_high,
>  						sda_falling_time,
>  						0,	/* DW default */
>  						0);	/* No offset */
> @@ -167,7 +186,7 @@ static int i2c_dw_set_timings_master(struct dw_i2c_dev *dev)
>  				i2c_dw_scl_lcnt(dev,
>  						DW_IC_HS_SCL_LCNT,
>  						ic_clk,
> -						320,	/* tLOW = 320 ns */
> +						t_low,

This looks fine to me.

Thanks,
Andi

>  						scl_falling_time,
>  						0);	/* No offset */
>  		}
> -- 
> 2.43.0
>