RE: [PATCH net-next 1/3] dt-bindings: net: emaclite: Add clock support

[Pandey, Radhey Shyam]

> -----Original Message-----
> From: Conor Dooley <conor@xxxxxxxxxx>
> Sent: Tuesday, October 1, 2024 10:22 PM
> To: Pandey, Radhey Shyam <radhey.shyam.pandey@xxxxxxx>
> Cc: davem@xxxxxxxxxxxxx; edumazet@xxxxxxxxxx; kuba@xxxxxxxxxx;
> pabeni@xxxxxxxxxx; robh@xxxxxxxxxx; krzk+dt@xxxxxxxxxx; conor+dt@xxxxxxxxxx;
> Simek, Michal <michal.simek@xxxxxxx>; Joseph, Abin <Abin.Joseph@xxxxxxx>;
> u.kleine-koenig@xxxxxxxxxxxxxx; elfring@xxxxxxxxxxxxxxxxxxxxx; Katakam, Harini
> <harini.katakam@xxxxxxx>; netdev@xxxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx;
> linux-kernel@xxxxxxxxxxxxxxx; linux-arm-kernel@xxxxxxxxxxxxxxxxxxx; git (AMD-Xilinx)
> <git@xxxxxxx>
> Subject: Re: [PATCH net-next 1/3] dt-bindings: net: emaclite: Add clock support
> 
> On Tue, Oct 01, 2024 at 01:25:36AM +0530, Radhey Shyam Pandey wrote:
> > From: Abin Joseph <abin.joseph@xxxxxxx>
> >
> > Add s_axi_aclk AXI4 clock support and make clk optional to keep DTB
> > backward compatibility. Define max supported clock constraints.
> 
> Why was the clock not provided before, but is now?
> Was it automatically enabled by firmware and that is no longer done?
> I'm suspicious of the clock being made optional, but the driver doing nothing other
> than enable it. That reeks of actually being required to me.

Traditionally these IP were used on microblaze platforms which had fixed
clocks enabled all the time. Since AXI Ethernet Lite is a PL IP, it can also
be used on SoC platforms like Zynq UltraScale+ MPSoC which combines 
processing system (PS) and user-programmable logic (PL) into the same 
device. On these platforms instead of fixed enabled clocks it is mandatory
to explicitly enable IP clocks for proper functionality. 

It gets more interesting when the PL clock is shared between two IPs 
and one of the drivers is clock adopted and disable the clocks after use 
and clock framework does not know about other clock users (emaclite 
IP using clock) and it will turn off the clocks which would lead to 
hang on emaclite reg access. So, it is needed to correctly model the
clock consumers.

While browsing i found a similar usecase for GMII to RGMII PL IP.
Similar to dt-bindings: net: xilinx_gmii2rgmii: Add clock support[1]
[1]: https://lore.kernel.org/all/4ae4d926-73f0-4f30-9d83-908a92046829@xxxxxxxxxx/

In this series - I noticed that Krzysztof suggested to:
Nope, just write the description as items in clocks, instead of
maxItems. And drop clock names, are not needed and are kind of obvious.

So something like the below would be fine?

+  clocks:
+    items:
+      - description: AXI4 clock.

> 
> >
> > Signed-off-by: Abin Joseph <abin.joseph@xxxxxxx>
> > Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xxxxxxx>
> > ---
> >  Documentation/devicetree/bindings/net/xlnx,emaclite.yaml | 3 +++
> >  1 file changed, 3 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/net/xlnx,emaclite.yaml
> > b/Documentation/devicetree/bindings/net/xlnx,emaclite.yaml
> > index 92d8ade988f6..8fcf0732d713 100644
> > --- a/Documentation/devicetree/bindings/net/xlnx,emaclite.yaml
> > +++ b/Documentation/devicetree/bindings/net/xlnx,emaclite.yaml
> > @@ -29,6 +29,9 @@ properties:
> >    interrupts:
> >      maxItems: 1
> >
> > +  clocks:
> > +    maxItems: 1
> > +
> >    phy-handle: true
> >
> >    local-mac-address: true
> > --
> > 2.34.1
> >