[PATCH v2] arm64: dts: marvell: cn9130-sr-som: fix cp0 mdio pin numbers

[Josua Mayer]

SolidRun CN9130 SoM actually uses CP_MPP[0:1] for mdio. CP_MPP[40]
provides reference clock for dsa switch and ethernet phy on Clearfog
Pro, wheras MPP[41] controls efuse programming voltage "VHV".

Update the cp0 mdio pinctrl node to specify mpp0, mpp1.

Fixes: 1c510c7d82e5 ("arm64: dts: add description for solidrun cn9130 som and clearfog boards")
Cc: stable@xxxxxxxxxxxxxxx # 6.11.x
Signed-off-by: Josua Mayer <josua@xxxxxxxxxxxxx>
---
Changes in v2:
- corrected Cc: stable list address
- removed duplicate "mdio" from commit message
- added Fixes: tag
- Link to v1: https://lore.kernel.org/r/20241002-cn9130-som-mdio-v1-1-0942be4dc550@xxxxxxxxxxxxx
---
 arch/arm64/boot/dts/marvell/cn9130-sr-som.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/marvell/cn9130-sr-som.dtsi b/arch/arm64/boot/dts/marvell/cn9130-sr-som.dtsi
index 4676e3488f54d53041696d877b510b8d51dcd984..cb8d54895a77753c760b58b8b5103149e21e2094 100644
--- a/arch/arm64/boot/dts/marvell/cn9130-sr-som.dtsi
+++ b/arch/arm64/boot/dts/marvell/cn9130-sr-som.dtsi
@@ -136,7 +136,7 @@ cp0_i2c0_pins: cp0-i2c0-pins {
 		};
 
 		cp0_mdio_pins: cp0-mdio-pins {
-			marvell,pins = "mpp40", "mpp41";
+			marvell,pins = "mpp0", "mpp1";
 			marvell,function = "ge";
 		};
 

---
base-commit: 9852d85ec9d492ebef56dc5f229416c925758edc
change-id: 20241002-cn9130-som-mdio-4a519e6dc7df

Best regards,
-- 
Josua Mayer <josua@xxxxxxxxxxxxx>