[tip: irq/urgent] irqchip/ocelot: Comment sticky register clearing code
From: tip-bot2 for Sergey Matsievskiy
Date: Wed Oct 02 2024 - 11:44:45 EST
The following commit has been merged into the irq/urgent branch of tip:
Commit-ID: 7f1f78b903c933617cbd352f9eafe9e3644f3b92
Gitweb: https://git.kernel.org/tip/7f1f78b903c933617cbd352f9eafe9e3644f3b92
Author: Sergey Matsievskiy <matsievskiysv@xxxxxxxxx>
AuthorDate: Wed, 25 Sep 2024 21:44:16 +03:00
Committer: Thomas Gleixner <tglx@xxxxxxxxxxxxx>
CommitterDate: Wed, 02 Oct 2024 15:11:07 +02:00
irqchip/ocelot: Comment sticky register clearing code
Add comment to the sticky register clearing code.
Signed-off-by: Sergey Matsievskiy <matsievskiysv@xxxxxxxxx>
Signed-off-by: Thomas Gleixner <tglx@xxxxxxxxxxxxx>
Link: https://lore.kernel.org/all/20240925184416.54204-3-matsievskiysv@xxxxxxxxx
---
drivers/irqchip/irq-mscc-ocelot.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/irqchip/irq-mscc-ocelot.c b/drivers/irqchip/irq-mscc-ocelot.c
index c19ab37..3dc745b 100644
--- a/drivers/irqchip/irq-mscc-ocelot.c
+++ b/drivers/irqchip/irq-mscc-ocelot.c
@@ -84,6 +84,12 @@ static void ocelot_irq_unmask(struct irq_data *data)
u32 val;
irq_gc_lock(gc);
+ /*
+ * Clear sticky bits for edge mode interrupts.
+ * Serval has only one trigger register replication, but the adjacent
+ * register is always read as zero, so there's no need to handle this
+ * case separately.
+ */
val = irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(p, 0)) |
irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(p, 1));
if (!(val & mask))