[PATCH 3/3] phy: samsung: gs101-ufs: Add hibern8 enter and exit specific tuning values

From: Peter Griffin
Date: Wed Oct 02 2024 - 16:16:56 EST


Add the gs101 specific phy calibration values that need to be programmed
when entering and exiting hibern8 state.

Signed-off-by: Peter Griffin <peter.griffin@xxxxxxxxxx>
---
drivers/phy/samsung/phy-gs101-ufs.c | 31 ++++++++++++++++++++++++++---
1 file changed, 28 insertions(+), 3 deletions(-)

diff --git a/drivers/phy/samsung/phy-gs101-ufs.c b/drivers/phy/samsung/phy-gs101-ufs.c
index 17b798da5b57..5363d8be6c76 100644
--- a/drivers/phy/samsung/phy-gs101-ufs.c
+++ b/drivers/phy/samsung/phy-gs101-ufs.c
@@ -108,10 +108,35 @@ static const struct samsung_ufs_phy_cfg tensor_gs101_post_pwr_hs_config[] = {
END_UFS_PHY_CFG,
};

+static const struct samsung_ufs_phy_cfg tensor_gs101_post_h8_enter[] = {
+ PHY_TRSV_REG_CFG_GS101(0x262, 0x08, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x265, 0x0A, PWR_MODE_ANY),
+ PHY_COMN_REG_CFG(0x1, 0x8, PWR_MODE_ANY),
+ PHY_COMN_REG_CFG(0x0, 0x86, PWR_MODE_ANY),
+ PHY_COMN_REG_CFG(0x8, 0x60, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x222, 0x08, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x246, 0x01, PWR_MODE_HS_ANY),
+ END_UFS_PHY_CFG,
+};
+
+static const struct samsung_ufs_phy_cfg tensor_gs101_pre_h8_exit[] = {
+ PHY_COMN_REG_CFG(0x0, 0xC6, PWR_MODE_ANY),
+ PHY_COMN_REG_CFG(0x1, 0x0C, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x262, 0x00, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x265, 0x00, PWR_MODE_ANY),
+ PHY_COMN_REG_CFG(0x8, 0xE0, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x246, 0x03, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x222, 0x18, PWR_MODE_HS_ANY),
+ END_UFS_PHY_CFG,
+};
+
+
static const struct samsung_ufs_phy_cfg *tensor_gs101_ufs_phy_cfgs[CFG_TAG_MAX] = {
- [CFG_PRE_INIT] = tensor_gs101_pre_init_cfg,
- [CFG_PRE_PWR_HS] = tensor_gs101_pre_pwr_hs_config,
- [CFG_POST_PWR_HS] = tensor_gs101_post_pwr_hs_config,
+ [CFG_PRE_INIT] = tensor_gs101_pre_init_cfg,
+ [CFG_PRE_PWR_HS] = tensor_gs101_pre_pwr_hs_config,
+ [CFG_POST_PWR_HS] = tensor_gs101_post_pwr_hs_config,
+ [CFG_POST_HIBERN8_ENTER] = tensor_gs101_post_h8_enter,
+ [CFG_PRE_HIBERN8_EXIT] = tensor_gs101_pre_h8_exit,
};

static const char * const tensor_gs101_ufs_phy_clks[] = {
--
2.46.1.824.gd892dcdcdd-goog