Re: [RFC PATCH 1/4] compiler.h: Introduce ptr_eq() to preserve address dependency

[Mathieu Desnoyers]

On 2024-10-03 02:08, Joel Fernandes wrote:
> On Tue, Oct 01, 2024 at 09:02:02PM -0400, Mathieu Desnoyers wrote:
> > Compiler CSE and SSA GVN optimizations can cause the address dependency
> > of addresses returned by rcu_dereference to be lost when comparing those
> > pointers with either constants or previously loaded pointers.
> >
> > Introduce ptr_eq() to compare two addresses while preserving the address
> > dependencies for later use of the address. It should be used when
> > comparing an address returned by rcu_dereference().
> >
> > This is needed to prevent the compiler CSE and SSA GVN optimizations
> > from using @a (or @b) in places where the source refers to @b (or @a)
> > based on the fact that after the comparison, the two are known to be
> > equal, which does not preserve address dependencies and allows the
> > following misordering speculations:
> >
> > - If @b is a constant, the compiler can issue the loads which depend
> >    on @a before loading @a.
> > - If @b is a register populated by a prior load, weakly-ordered
> >    CPUs can speculate loads which depend on @a before loading @a.
> >
> > The same logic applies with @a and @b swapped.
> [...]
> > +/*
> > + * Compare two addresses while preserving the address dependencies for
> > + * later use of the address. It should be used when comparing an address
> > + * returned by rcu_dereference().
> > + *
> > + * This is needed to prevent the compiler CSE and SSA GVN optimizations
> > + * from using @a (or @b) in places where the source refers to @b (or @a)
> > + * based on the fact that after the comparison, the two are known to be
> > + * equal, which does not preserve address dependencies and allows the
> > + * following misordering speculations:
> > + *
> > + * - If @b is a constant, the compiler can issue the loads which depend
> > + *   on @a before loading @a.
> > + * - If @b is a register populated by a prior load, weakly-ordered
> > + *   CPUs can speculate loads which depend on @a before loading @a.
> > + *
> > + * The same logic applies with @a and @b swapped.
> > + *
> > + * Return value: true if pointers are equal, false otherwise.
> > + *
> > + * The compiler barrier() is ineffective at fixing this issue. It does
> > + * not prevent the compiler CSE from losing the address dependency:
> > + *
> > + * int fct_2_volatile_barriers(void)
> > + * {
> > + *     int *a, *b;
> > + *
> > + *     do {
> > + *         a = READ_ONCE(p);
> > + *         asm volatile ("" : : : "memory");
> > + *         b = READ_ONCE(p);
> > + *     } while (a != b);
> > + *     asm volatile ("" : : : "memory");  <-- barrier()
> > + *     return *b;
> > + * }
> > + *
> > + * With gcc 14.2 (arm64):
> > + *
> > + * fct_2_volatile_barriers:
> > + *         adrp    x0, .LANCHOR0
> > + *         add     x0, x0, :lo12:.LANCHOR0
> > + * .L2:
> > + *         ldr     x1, [x0]  <-- x1 populated by first load.
> > + *         ldr     x2, [x0]
> > + *         cmp     x1, x2
> > + *         bne     .L2
> > + *         ldr     w0, [x1]  <-- x1 is used for access which should depend on b.
> > + *         ret
> > + *
>
> I could reproduce this in compiler explorer, but I'm curious what flags are
> you using? For me it does a bunch of usage of the stack for temporary storage
> (still incorrectly returns *a though as you pointed).

You are probably missing "-O2".


> Interestingly, if I just move the comparison into an an __always_inline__
> function like below, but without the optimizer hide stuff, gcc 14.2 on arm64
> does generate the correct code:

Make sure you compile in -O2. Based on a quick check here the hide var
is needed to make sure the compiler does the intended behavior in O2.

> static inline __attribute__((__always_inline__)) int ptr_eq(const volatile void *a, const volatile void *b)
> {
>      /* No OPTIMIZER_HIDE_VAR */
>      return a == b;
> }
>
> volatile int *p = 0;
>
> int fct_2_volatile_barriers()
> {
>      int *a, *b;
>
>      do {
>          a = READ_ONCE(p);
>          asm volatile ("" : : : "memory");
>          b = READ_ONCE(p);
>      } while (!ptr_eq(a, b));
>      asm volatile ("" : : : "memory");  // barrier()
>      return *b;
> }
>
> But not sure if it fixes the speculation issue you referred to.

Not in -O2.

> Putting back the OPTIMIZER_HIDE_VAR() then just seems to pass the a and b
> stored on the stack through a washing machine:
>
>          ldr     x0, [sp, 8]
>          str     x0, [sp, 8]
>          ldr     x0, [sp]
>          str     x0, [sp]

That washing machine looks like the result of -O0.

> And here I thought the "" in OPTIMIZER_HIDE_VAR was not supposed to generate
> any code but I guess it is still a NOOP.

The hide var will only emit an extra register movement to copy the
register to a temporary. That's one extra instruction but not as bad
as what you observe in -O0.

> Anyway, as such this LGTM since whether OPTIMIZER_HIDE_VAR() used or not, it
> does fix the problem.

hide var is needed in O2.

> Reviewed-by: Joel Fernandes (Google) <joel@xxxxxxxxxxxxxxxxx>

Please double-check with -O2, and let me know if you still agree with
the patch :)

Thanks,

Mathieu


> thanks,
>
>   - Joel

--
Mathieu Desnoyers
EfficiOS Inc.
https://www.efficios.com