[PATCH v8 00/12] Preemption support for A7XX
From: Antonino Maniscalco
Date: Thu Oct 03 2024 - 12:13:08 EST
This series implements preemption for A7XX targets, which allows the GPU to
switch to an higher priority ring when work is pushed to it, reducing latency
for high priority submissions.
This series enables L1 preemption with skip_save_restore which requires
the following userspace patches to function:
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544
A flag is added to `msm_submitqueue_create` to only allow submissions
from compatible userspace to be preempted, therefore maintaining
compatibility.
Preemption is currently only enabled by default on A750, it can be
enabled on other targets through the `enable_preemption` module
parameter. This is because more testing is required on other targets.
For testing on other HW it is sufficient to set that parameter to a
value of 1, then using the branch of mesa linked above, `TU_DEBUG=hiprio`
allows to run any application as high priority therefore preempting
submissions from other applications.
The `msm_gpu_preemption_trigger` and `msm_gpu_preemption_irq` traces
added in this series can be used to observe preemption's behavior as
well as measuring preemption latency.
Some commits from this series are based on a previous series to enable
preemption on A6XX targets:
https://lkml.kernel.org/1520489185-21828-1-git-send-email-smasetty@xxxxxxxxxxxxxx
Signed-off-by: Antonino Maniscalco <antomani103@xxxxxxxxx>
---
Changes in v8:
- Updated commit message on 11/12 to reflect the fact that we are
enabling on more targets
- Fixed typo in documentation
- Link to v7: https://lore.kernel.org/r/20240930-preemption-a750-t-v7-0-47803c7a5a64@xxxxxxxxx
Changes in v7:
- Enable preemption on more targets
- Move pwrup reglist to a6xx_catalog and get rid of ifpc list
- Split out smmu_info from preemption record in separate GPU_RO
allocation
- Make postmable buffer GPU_RO
- Link to v6: https://lore.kernel.org/r/20240926-preemption-a750-t-v6-0-7b6e1ef3648f@xxxxxxxxx
Changes in v6:
- Fixed commit message prefix (A6XX->a6xx)
- Allow preemption to be disabled at run time
- Link to v5: https://lore.kernel.org/r/20240924-preemption-a750-t-v5-0-0be2bf81c187@xxxxxxxxx
Changes in v5:
- Made preemption documentation more detailed
- Added ring ID to preempt_record BO name
- Added Neil's Tested-By tags
- Added Akhil's Reviewed-By tags
- Added Rob's Tested-By tags
- Moved preemption module params to adreno_device.c
- Link to v4: https://lore.kernel.org/r/20240917-preemption-a750-t-v4-0-95d48012e0ac@xxxxxxxxx
Changes in v4:
- Added missing register in pwrup list
- Removed and rearrange barriers
- Renamed `skip_inline_wptr` to `restore_wptr`
- Track ctx seqno per ring
- Removed secure preempt context
- NOP out postamble to disable it instantly
- Only emit pwrup reglist once
- Document bv_rptr_addr
- Removed unused A6XX_PREEMPT_USER_RECORD_SIZE
- Set name on preempt record buffer
- Link to v3: https://lore.kernel.org/r/20240905-preemption-a750-t-v3-0-fd947699f7bc@xxxxxxxxx
Changes in v3:
- Added documentation about preemption
- Use quirks to determine which target supports preemption
- Add a module parameter to force disabling or enabling preemption
- Clear postamble when profiling
- Define A6XX_CP_CONTEXT_SWITCH_CNTL_LEVEL fields in a6xx.xml
- Make preemption records MAP_PRIV
- Removed user ctx record (NON_PRIV) and patch 2/9 as it's not needed
anymore
- Link to v2: https://lore.kernel.org/r/20240830-preemption-a750-t-v2-0-86aeead2cd80@xxxxxxxxx
Changes in v2:
- Added preept_record_size for X185 in PATCH 3/7
- Added patches to reset perf counters
- Dropped unused defines
- Dropped unused variable (fixes warning)
- Only enable preemption on a750
- Reject MSM_SUBMITQUEUE_ALLOW_PREEMPT for unsupported targets
- Added Akhil's Reviewed-By tags to patches 1/9,2/9,3/9
- Added Neil's Tested-By tags
- Added explanation for UAPI changes in commit message
- Link to v1: https://lore.kernel.org/r/20240815-preemption-a750-t-v1-0-7bda26c34037@xxxxxxxxx
---
Antonino Maniscalco (12):
drm/msm: Fix bv_fence being used as bv_rptr
drm/msm/a6xx: Track current_ctx_seqno per ring
drm/msm: Add a `preempt_record_size` field
drm/msm: Add CONTEXT_SWITCH_CNTL bitfields
drm/msm/a6xx: Add a pwrup_list field to a6xx_info
drm/msm/a6xx: Implement preemption for a7xx targets
drm/msm/a6xx: Sync relevant adreno_pm4.xml changes
drm/msm/a6xx: Use posamble to reset counters on preemption
drm/msm/a6xx: Add traces for preemption
drm/msm/a6xx: Add a flag to allow preemption to submitqueue_create
drm/msm/a6xx: Enable preemption for tested a7xx targets
Documentation: document adreno preemption
Documentation/gpu/msm-preemption.rst | 99 +++++
drivers/gpu/drm/msm/Makefile | 1 +
drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 2 +-
drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 2 +-
drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 2 +-
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 6 +-
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 42 +-
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 235 ++++++++++-
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 170 ++++++++
drivers/gpu/drm/msm/adreno/a6xx_preempt.c | 457 +++++++++++++++++++++
drivers/gpu/drm/msm/adreno/adreno_device.c | 4 +
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 22 +-
drivers/gpu/drm/msm/msm_gpu.c | 2 +-
drivers/gpu/drm/msm/msm_gpu.h | 11 -
drivers/gpu/drm/msm/msm_gpu_trace.h | 28 ++
drivers/gpu/drm/msm/msm_ringbuffer.h | 18 +
drivers/gpu/drm/msm/msm_submitqueue.c | 7 +
drivers/gpu/drm/msm/registers/adreno/a6xx.xml | 7 +-
.../gpu/drm/msm/registers/adreno/adreno_pm4.xml | 39 +-
include/uapi/drm/msm_drm.h | 5 +-
20 files changed, 1090 insertions(+), 69 deletions(-)
---
base-commit: 7c626ce4bae1ac14f60076d00eafe71af30450ba
change-id: 20240815-preemption-a750-t-fcee9a844b39
Best regards,
--
Antonino Maniscalco <antomani103@xxxxxxxxx>