[GIT PULL] spi-mem/swap16 changes for v6.13

[Tudor Ambarus]

Hi, Mark,

I've made an immutable tag for the spi-mem swap16 changes. I let the
0day bot run on them, I got no complains. Pull if you need them.

Thanks,
ta

The following changes since commit 9852d85ec9d492ebef56dc5f229416c925758edc:

  Linux 6.12-rc1 (2024-09-29 15:06:19 -0700)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git
tags/mtd/spi-mem-swap16-for-6.13

for you to fetch changes up to 50cb86f21ec2ede08d0ec0479fbd8697a8a25616:

  spi: mxic: Add support for swapping byte (2024-10-02 09:44:57 +0300)

----------------------------------------------------------------
This allows specifying the byte order in Octal DTR mode.

There are NOR flashes (Macronix) that swap the bytes on a 16-bit
boundary when configured in Octal DTR mode. The byte order of
16-bit words is swapped when read or written in Octal Double
Transfer Rate (DTR) mode compared to Single Transfer Rate (STR)
modes. If one writes D0 D1 D2 D3 bytes using 1-1-1 mode, and uses
8D-8D-8D SPI mode for reading, it will read back D1 D0 D3 D2.
Swapping the bytes may introduce some endianness problems. It can
affect the boot sequence if the entire boot sequence is not handled
in either 8D-8D-8D mode or 1-1-1 mode. Therefore, it is necessary
to swap the bytes back to ensure the same byte order as in STR modes.
Fortunately there are controllers that could swap the bytes back at
runtime, addressing the flash's endianness requirements. Provide a
way for the upper layers to specify the byte order in Octal DTR mode.

----------------------------------------------------------------
AlvinZhou (1):
      spi: mxic: Add support for swapping byte

Tudor Ambarus (1):
      spi: spi-mem: Allow specifying the byte order in Octal DTR mode

 drivers/spi/spi-mem.c       |  3 +++
 drivers/spi/spi-mxic.c      | 17 +++++++++++++----
 include/linux/spi/spi-mem.h |  8 +++++++-
 3 files changed, 23 insertions(+), 5 deletions(-)