Re: [PATCH v4 0/3] riscv: Per-thread envcfg CSR support

[patchwork-bot+linux-riscv]

Hello:

This series was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <palmer@xxxxxxxxxxxx>:

On Wed, 14 Aug 2024 01:10:53 -0700 you wrote:
> This series (or equivalent) is a prerequisite for both user-mode pointer
> masking and CFI support, as both of those are per-thread features and
> are controlled by fields in the envcfg CSR. These patches are based on
> v1 of the pointer masking series[1], with significant input from both
> Deepak and Andrew.
> 
> [1]: https://lore.kernel.org/linux-riscv/20240319215915.832127-6-samuel.holland@xxxxxxxxxx/
> 
> [...]

Here is the summary with links:
  - [v4,1/3] riscv: Enable cbo.zero only when all harts support Zicboz
    https://git.kernel.org/riscv/c/1b57747e978f
  - [v4,2/3] riscv: Add support for per-thread envcfg CSR values
    https://git.kernel.org/riscv/c/5fc7355f0137
  - [v4,3/3] riscv: Call riscv_user_isa_enable() only on the boot hart
    https://git.kernel.org/riscv/c/368546ebe7e7

You are awesome, thank you!
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