shift and mask issue in drivers/gpu/drm/sprd/megacores_pll.c

[Colin King (gmail)]

Hi,

I noticed a shift/mask issue in dphy_set_pll_reg() in 
drivers/gpu/drm/sprd/megacores_pll.c, the expression (pll->kint << 4) & 
0xf is
always zero:

        ...
        reg_val[4] = pll->kint >> 12;
        reg_val[5] = pll->kint >> 4;
        reg_val[6] = pll->out_sel | ((pll->kint << 4) & 0xf);
        ...

I'm not sure what the correct expression should be, but the current 
assignment to reg_val[6] seems incorrect to me.

Colin