Re: [PATCH net-next 1/3] net: phy: realtek: read duplex and gbit master from PHYSR register

[Daniel Golle]

On Wed, Oct 09, 2024 at 11:01:59AM +0100, Russell King (Oracle) wrote:
> On Wed, Oct 09, 2024 at 02:53:03AM +0100, Daniel Golle wrote:
> > -static void rtlgen_decode_speed(struct phy_device *phydev, int val)
> > +static void rtlgen_decode_physr(struct phy_device *phydev, int val)
> >  {
> > -	switch (val & RTLGEN_SPEED_MASK) {
> > +	/* bit 2
> > +	 * 0: Link not OK
> > +	 * 1: Link OK
> > +	 */
> > +	phydev->link = !!(val & RTL_VND2_PHYSR_LINK);
> 
> Be careful with this. The link status bit in the BMSR is latched-low,
> meaning that it guarantees to inform the reader that the link failed at
> some point between the preceding read and current read.
> 
> This is important to know, so code can react to a possibly different
> negotiation result (we must see a link-fail to recognise a different
> set of negotiation results.)

The datasheet calls that bit "Real Time Link Status".
If you think we should not use it, I will drop it.