Re: [PATCH] arm64: dts: broadcom: Fix L2 linesize for Raspberry Pi 5

[Conor Dooley]

On Thu, Oct 10, 2024 at 11:04:07AM -0400, Willow Cunningham wrote:
> From: Willow Cunningham <willow.e.cunningham@xxxxxxxxx>
> 
> Fixes: faa3381267d0 ("arm64: dts: broadcom: Add minimal support for
> Raspberry Pi 5")

This btw Willow, is meant to be...

> 
> Set the cache-line-size parameter of the L2 cache for each core to the
> correct value of 64 bytes.
> 
> Previously, the L2 cache line size was incorrectly set to 128 bytes
> for the Broadcom BCM2712. This causes validation tests for the
> Performance Application Programming Interface (PAPI) tool to fail as
> they depend on sysfs accurately reporting cache line sizes.
> 
> The correct value of 64 bytes is stated in the official documentation of
> the ARM Cortex A-72, which is linked in the comments of
> arm64/boot/dts/broadcom/bcm2712.dtsi as the source for cache-line-size.
> 

> Signed-off-by: Willow Cunningham <willow.e.cunningham@xxxxxxxxx>

Down here, on the line before your signoff. Perhaps Florian is willing
to fix that for you though.

Cheers,
Conor.

> ---
>  arch/arm64/boot/dts/broadcom/bcm2712.dtsi | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
> index 6e5a984c1d4e..26a29e5e5078 100644
> --- a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
> +++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
> @@ -67,7 +67,7 @@ cpu0: cpu@0 {
>  			l2_cache_l0: l2-cache-l0 {
>  				compatible = "cache";
>  				cache-size = <0x80000>;
> -				cache-line-size = <128>;
> +				cache-line-size = <64>;
>  				cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
>  				cache-level = <2>;
>  				cache-unified;
> @@ -91,7 +91,7 @@ cpu1: cpu@1 {
>  			l2_cache_l1: l2-cache-l1 {
>  				compatible = "cache";
>  				cache-size = <0x80000>;
> -				cache-line-size = <128>;
> +				cache-line-size = <64>;
>  				cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
>  				cache-level = <2>;
>  				cache-unified;
> @@ -115,7 +115,7 @@ cpu2: cpu@2 {
>  			l2_cache_l2: l2-cache-l2 {
>  				compatible = "cache";
>  				cache-size = <0x80000>;
> -				cache-line-size = <128>;
> +				cache-line-size = <64>;
>  				cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
>  				cache-level = <2>;
>  				cache-unified;
> @@ -139,7 +139,7 @@ cpu3: cpu@3 {
>  			l2_cache_l3: l2-cache-l3 {
>  				compatible = "cache";
>  				cache-size = <0x80000>;
> -				cache-line-size = <128>;
> +				cache-line-size = <64>;
>  				cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
>  				cache-level = <2>;
>  				cache-unified;
> -- 
> 2.39.2
>

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