SG2044 relys on an internal divisor when calculating bitrate, which
means a wrong clock for the most common bitrates. So a quirk is needed
for this uart device to skip the set rate call and only relys on the
internal UART divisor.
Inochi Amaoto (2):
dt-bindings: serial: snps-dw-apb-uart: Add Sophgo SG2044 uarts
serial: 8250_dw: Add Sophgo SG2044 quirk
.../devicetree/bindings/serial/snps-dw-apb-uart.yaml | 4 ++++
drivers/tty/serial/8250/8250_dw.c | 6 ++++++
2 files changed, 10 insertions(+)
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2.47.0