Re: [PATCH v3] clk: qcom: clk-alpha-pll: Fix pll post div mask when width is not set

[Christopher Obbard]

On Sun, 6 Oct 2024 at 21:52, Barnabás Czémán
<barnabas.czeman@xxxxxxxxxxxxxx> wrote:
> Many qcom clock drivers do not have .width set. In that case value of
> (p)->width - 1 will be negative which breaks clock tree. Fix this
> by checking if width is zero, and pass 3 to GENMASK if that's the case.
>
> Fixes: 1c3541145cbf ("clk: qcom: support for 2 bit PLL post divider")
> Signed-off-by: Barnabás Czémán <barnabas.czeman@xxxxxxxxxxxxxx>
> ---
> Changes in v3:
> - Remove one of the fixes tag.
> - Link to v2: https://lore.kernel.org/r/20240925-fix-postdiv-mask-v2-1-b825048b828b@xxxxxxxxxxxxxx
>
> Changes in v2:
> - Pass 3 to GENMASK instead of 0.
> - Add more Fixes tag for reference root cause.
> - Link to v1: https://lore.kernel.org/r/20240925-fix-postdiv-mask-v1-1-f70ba55f415e@xxxxxxxxxxxxxx
> ---
>  drivers/clk/qcom/clk-alpha-pll.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Hi Barnabás,

This patch fixes a regression with UFS devfreq on msm8996 (introduced
with the linked commit in your patch) so:

Reviewed-by: Christopher Obbard <christopher.obbard@xxxxxxxxxx>
Tested-by: Christopher Obbard <christopher.obbard@xxxxxxxxxx>