Re: [PATCH v3 2/3] pwm: sophgo: add driver for Sophgo SG2042 PWM

[Chen Wang]

On 2024/10/8 16:24, Sean Young wrote:
> On Tue, Oct 08, 2024 at 11:04:14AM +0800, Chen Wang wrote:
> > From: Chen Wang <unicorn_wang@xxxxxxxxxxx>
> >
> > Add a PWM driver for PWM controller in Sophgo SG2042 SoC.
[......]
> > +static int pwm_sg2042_probe(struct platform_device *pdev)
> > +{
> > +	struct device *dev = &pdev->dev;
> > +	struct sg2042_pwm_ddata *ddata;
> > +	struct pwm_chip *chip;
> > +	struct clk *clk;
> > +	int ret;
> > +
> > +	chip = devm_pwmchip_alloc(dev, SG2042_PWM_CHANNELNUM, sizeof(*ddata));
> > +	if (IS_ERR(chip))
> > +		return PTR_ERR(chip);
> > +	ddata = pwmchip_get_drvdata(chip);
> > +
> > +	ddata->base = devm_platform_ioremap_resource(pdev, 0);
> > +	if (IS_ERR(ddata->base))
> > +		return PTR_ERR(ddata->base);
> > +
> > +	clk = devm_clk_get_enabled(dev, "apb");
> > +	if (IS_ERR(clk))
> > +		return dev_err_probe(dev, PTR_ERR(clk), "failed to get base clk\n");
> > +
> > +	ret = devm_clk_rate_exclusive_get(dev, clk);
> > +	if (ret)
> > +		return dev_err_probe(dev, ret, "failed to get exclusive rate\n");
> > +
> > +	ddata->clk_rate_hz = clk_get_rate(clk);
> > +	if (!ddata->clk_rate_hz || ddata->clk_rate_hz > NSEC_PER_SEC)
> > +		return dev_err_probe(dev, -EINVAL,
> > +				     "Invalid clock rate: %lu\n", ddata->clk_rate_hz);
> > +
> > +	chip->ops = &pwm_sg2042_ops;
> I think you can add here:
>
> 	chip->atomic = true;
>
> As far as I can see, the driver does not do any sleeping operations
> in pwm_sg2042_apply(). This probably should be tested with
> CONFIG_PWM_DEBUG and CONFIG_DEBUG_ATOMIC_SLEEP just to be sure.
>
> Thanks,
> Sean

Thank you Sean. We don't sleep when apply, so atomic should be needed.

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