Re: [PATCH] drm/msm/dpu: Don't always set merge_3d pending flush

[Jessica Zhang]

On 10/10/2024 8:20 AM, Dmitry Baryshkov wrote:
> On Wed, Oct 09, 2024 at 08:41:13PM GMT, Jessica Zhang wrote:
> > Don't set the merge_3d pending flush bits if the mode_3d is
> > BLEND_3D_NONE.
> >
> > Always flushing merge_3d can cause timeout issues when there are
> > multiple commits with concurrent writeback enabled.
> >
> > This is because the video phys enc waits for the hw_ctl flush register
> > to be completely cleared [1] in its wait_for_commit_done(), but the WB
> > encoder always sets the merge_3d pending flush during each commit
> > regardless of if the merge_3d is actually active.
> >
> > This means that the hw_ctl flush register will never be 0 when there are
> > multiple CWB commits and the video phys enc will hit vblank timeout
> > errors after the first CWB commit.
>
>  From this description, wouldn't it be more correct to always set
> intf_cfg.merge_3d in WB code (even if mode_3d is NONE)?

Hi Dmitry,

This discussion should be addressed in [1].

Thanks,

Jessica Zhang

[1] https://patchwork.freedesktop.org/series/139824/

> > [1] commit fe9df3f50c39 ("drm/msm/dpu: add real wait_for_commit_done()")
> >
> > Fixes: 3e79527a33a8 ("drm/msm/dpu: enable merge_3d support on sm8150/sm8250")
> > Fixes: d7d0e73f7de3 ("drm/msm/dpu: introduce the dpu_encoder_phys_* for writeback")
> > Signed-off-by: Jessica Zhang <quic_jesszhan@xxxxxxxxxxx>
> > ---
> >   drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 5 ++++-
> >   drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c  | 5 ++++-
> >   2 files changed, 8 insertions(+), 2 deletions(-)
>
> --
> With best wishes
> Dmitry