Re: [PATCH v4 5/9] misc: amd-sbi: Add support for mailbox error codes

[Gupta, Akshay]

On 10/13/2024 8:49 PM, Greg KH wrote:
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>
> On Thu, Sep 12, 2024 at 07:08:06AM +0000, Akshay Gupta wrote:
> > --- a/include/uapi/misc/amd-apml.h
> > +++ b/include/uapi/misc/amd-apml.h
> > @@ -38,6 +38,10 @@ struct apml_message {
> >                __u32 mb_in[2];
> >                __u8 reg_in[8];
> >        } data_in;
> > +     /*
> > +      * Error code is returned in case of soft mailbox
> > +      */
> > +     __u32 fw_ret_code;
> >   } __attribute__((packed));
> You can not just randomly change the size of a user/kernel structure
> like this, what just broke because of this?
>
> confused,

The changes are not because of anything is broken, we support 3 
different protocol under 1 IOCTL using the same structure. I split the 
patch to make it easy to review.
Modification in patch 4, is only for the existing code. This patch 
(patch 5) has additional functionality, so we do not want add multiple 
changes in single patch (patch 4).

The changes done in patches are as follows:

Patch 4:

- Adding basic structure as per current protocol in upstream kernel

Patch 5:

- Adding additional error code from PMFW.

Patch 6:

- Add changes required to support CPUID protocol

Patch 7:

- Comments modification for MCAMSR protocol (structure remains same as 
CPUID)

> greg k-h