[PATCH v1 2/5] arm64: dts: qcom: Add support for configuring channel TRE size

From: Jyothi Kumar Seerapu
Date: Tue Oct 15 2024 - 08:09:21 EST

Next message: Jyothi Kumar Seerapu: "[PATCH v1 3/5] dmaengine: qcom: gpi: Add provision to support TRE size as the fourth argument of dma-cells property"
Previous message: Jyothi Kumar Seerapu: "[PATCH v1 1/5] dt-bindings: dmaengine: qcom: gpi: Add additional arg to dma-cell property"
In reply to: Rob Herring: "Re: [PATCH v1 1/5] dt-bindings: dmaengine: qcom: gpi: Add additional arg to dma-cell property"
Next in thread: Krzysztof Kozlowski: "Re: [PATCH v1 2/5] arm64: dts: qcom: Add support for configuring channel TRE size"
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When high performance with multiple i2c messages in a single transfer
is required, employ Block Event Interrupt (BEI) to trigger interrupts
after specific messages transfer and the last message transfer,
thereby reducing interrupts.
For each i2c message transfer, a series of Transfer Request Elements(TREs)
must be programmed, including config tre for frequency configuration,
go tre for holding i2c address and dma tre for holding dma buffer address,
length as per the hardware programming guide. For transfer using BEI,
multiple I2C messages may necessitate the preparation of config, go,
and tx DMA TREs. However, a channel TRE size of 64 is often insufficient,
potentially leading to failures due to inadequate memory space.

Adjust the channel TRE size through the device tree.
The default size is 64, but clients can modify this value based on
their heigher channel TRE size requirements.

Signed-off-by: Jyothi Kumar Seerapu <quic_jseerapu@xxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 132 +++++++++++++--------------
1 file changed, 66 insertions(+), 66 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 3d8410683402..c7c0e15ff9d3 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -1064,7 +1064,7 @@
};

gpi_dma0: dma-controller@900000 {
- #dma-cells = <3>;
+ #dma-cells = <4>;
compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma";
reg = <0 0x00900000 0 0x60000>;
interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
@@ -1114,8 +1114,8 @@
"qup-memory";
power-domains = <&rpmhpd SC7280_CX>;
required-opps = <&rpmhpd_opp_low_svs>;
- dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
- <&gpi_dma0 1 0 QCOM_GPI_I2C>;
+ dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C 64>,
+ <&gpi_dma0 1 0 QCOM_GPI_I2C 64>;
dma-names = "tx", "rx";
status = "disabled";
};
@@ -1135,8 +1135,8 @@
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
interconnect-names = "qup-core", "qup-config";
- dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
- <&gpi_dma0 1 0 QCOM_GPI_SPI>;
+ dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI 64>,
+ <&gpi_dma0 1 0 QCOM_GPI_SPI 64>;
dma-names = "tx", "rx";
status = "disabled";
};
@@ -1174,8 +1174,8 @@
"qup-memory";
power-domains = <&rpmhpd SC7280_CX>;
required-opps = <&rpmhpd_opp_low_svs>;
- dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
- <&gpi_dma0 1 1 QCOM_GPI_I2C>;
+ dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C 64>,
+ <&gpi_dma0 1 1 QCOM_GPI_I2C 64>;
dma-names = "tx", "rx";
status = "disabled";
};
@@ -1195,8 +1195,8 @@
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
interconnect-names = "qup-core", "qup-config";
- dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
- <&gpi_dma0 1 1 QCOM_GPI_SPI>;
+ dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI 64>,
+ <&gpi_dma0 1 1 QCOM_GPI_SPI 64>;
dma-names = "tx", "rx";
status = "disabled";
};
@@ -1234,8 +1234,8 @@
"qup-memory";
power-domains = <&rpmhpd SC7280_CX>;
required-opps = <&rpmhpd_opp_low_svs>;
- dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
- <&gpi_dma0 1 2 QCOM_GPI_I2C>;
+ dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C 64>,
+ <&gpi_dma0 1 2 QCOM_GPI_I2C 64>;
dma-names = "tx", "rx";
status = "disabled";
};
@@ -1255,8 +1255,8 @@
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
interconnect-names = "qup-core", "qup-config";
- dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
- <&gpi_dma0 1 2 QCOM_GPI_SPI>;
+ dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI 64>,
+ <&gpi_dma0 1 2 QCOM_GPI_SPI 64>;
dma-names = "tx", "rx";
status = "disabled";
};
@@ -1294,8 +1294,8 @@
"qup-memory";
power-domains = <&rpmhpd SC7280_CX>;
required-opps = <&rpmhpd_opp_low_svs>;
- dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
- <&gpi_dma0 1 3 QCOM_GPI_I2C>;
+ dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C 64>,
+ <&gpi_dma0 1 3 QCOM_GPI_I2C 64>;
dma-names = "tx", "rx";
status = "disabled";
};
@@ -1315,8 +1315,8 @@
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
interconnect-names = "qup-core", "qup-config";
- dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
- <&gpi_dma0 1 3 QCOM_GPI_SPI>;
+ dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI 64>,
+ <&gpi_dma0 1 3 QCOM_GPI_SPI 64>;
dma-names = "tx", "rx";
status = "disabled";
};
@@ -1354,8 +1354,8 @@
"qup-memory";
power-domains = <&rpmhpd SC7280_CX>;
required-opps = <&rpmhpd_opp_low_svs>;
- dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
- <&gpi_dma0 1 4 QCOM_GPI_I2C>;
+ dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C 64>,
+ <&gpi_dma0 1 4 QCOM_GPI_I2C 64>;
dma-names = "tx", "rx";
status = "disabled";
};
@@ -1375,8 +1375,8 @@
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
interconnect-names = "qup-core", "qup-config";
- dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
- <&gpi_dma0 1 4 QCOM_GPI_SPI>;
+ dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI 64>,
+ <&gpi_dma0 1 4 QCOM_GPI_SPI 64>;
dma-names = "tx", "rx";
status = "disabled";
};
@@ -1414,8 +1414,8 @@
"qup-memory";
power-domains = <&rpmhpd SC7280_CX>;
required-opps = <&rpmhpd_opp_low_svs>;
- dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
- <&gpi_dma0 1 5 QCOM_GPI_I2C>;
+ dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C 64>,
+ <&gpi_dma0 1 5 QCOM_GPI_I2C 64>;
dma-names = "tx", "rx";
status = "disabled";
};
@@ -1435,8 +1435,8 @@
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
interconnect-names = "qup-core", "qup-config";
- dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
- <&gpi_dma0 1 5 QCOM_GPI_SPI>;
+ dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI 64>,
+ <&gpi_dma0 1 5 QCOM_GPI_SPI 64>;
dma-names = "tx", "rx";
status = "disabled";
};
@@ -1474,8 +1474,8 @@
"qup-memory";
power-domains = <&rpmhpd SC7280_CX>;
required-opps = <&rpmhpd_opp_low_svs>;
- dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
- <&gpi_dma0 1 6 QCOM_GPI_I2C>;
+ dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C 64>,
+ <&gpi_dma0 1 6 QCOM_GPI_I2C 64>;
dma-names = "tx", "rx";
status = "disabled";
};
@@ -1495,8 +1495,8 @@
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
interconnect-names = "qup-core", "qup-config";
- dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
- <&gpi_dma0 1 6 QCOM_GPI_SPI>;
+ dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI 64>,
+ <&gpi_dma0 1 6 QCOM_GPI_SPI 64>;
dma-names = "tx", "rx";
status = "disabled";
};
@@ -1534,8 +1534,8 @@
"qup-memory";
power-domains = <&rpmhpd SC7280_CX>;
required-opps = <&rpmhpd_opp_low_svs>;
- dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
- <&gpi_dma0 1 7 QCOM_GPI_I2C>;
+ dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C 64>,
+ <&gpi_dma0 1 7 QCOM_GPI_I2C 64>;
dma-names = "tx", "rx";
status = "disabled";
};
@@ -1555,8 +1555,8 @@
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
interconnect-names = "qup-core", "qup-config";
- dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
- <&gpi_dma0 1 7 QCOM_GPI_SPI>;
+ dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI 64>,
+ <&gpi_dma0 1 7 QCOM_GPI_SPI 64>;
dma-names = "tx", "rx";
status = "disabled";
};
@@ -1579,7 +1579,7 @@
};

gpi_dma1: dma-controller@a00000 {
- #dma-cells = <3>;
+ #dma-cells = <4>;
compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma";
reg = <0 0x00a00000 0 0x60000>;
interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
@@ -1629,8 +1629,8 @@
"qup-memory";
power-domains = <&rpmhpd SC7280_CX>;
required-opps = <&rpmhpd_opp_low_svs>;
- dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
- <&gpi_dma1 1 0 QCOM_GPI_I2C>;
+ dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C 64>,
+ <&gpi_dma1 1 0 QCOM_GPI_I2C 64>;
dma-names = "tx", "rx";
status = "disabled";
};
@@ -1650,8 +1650,8 @@
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
interconnect-names = "qup-core", "qup-config";
- dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
- <&gpi_dma1 1 0 QCOM_GPI_SPI>;
+ dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI 64>,
+ <&gpi_dma1 1 0 QCOM_GPI_SPI 64>;
dma-names = "tx", "rx";
status = "disabled";
};
@@ -1689,8 +1689,8 @@
"qup-memory";
power-domains = <&rpmhpd SC7280_CX>;
required-opps = <&rpmhpd_opp_low_svs>;
- dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
- <&gpi_dma1 1 1 QCOM_GPI_I2C>;
+ dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C 64>,
+ <&gpi_dma1 1 1 QCOM_GPI_I2C 64>;
dma-names = "tx", "rx";
status = "disabled";
};
@@ -1710,8 +1710,8 @@
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
interconnect-names = "qup-core", "qup-config";
- dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
- <&gpi_dma1 1 1 QCOM_GPI_SPI>;
+ dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI 64>,
+ <&gpi_dma1 1 1 QCOM_GPI_SPI 64>;
dma-names = "tx", "rx";
status = "disabled";
};
@@ -1749,8 +1749,8 @@
"qup-memory";
power-domains = <&rpmhpd SC7280_CX>;
required-opps = <&rpmhpd_opp_low_svs>;
- dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
- <&gpi_dma1 1 2 QCOM_GPI_I2C>;
+ dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C 64>,
+ <&gpi_dma1 1 2 QCOM_GPI_I2C 64>;
dma-names = "tx", "rx";
status = "disabled";
};
@@ -1770,8 +1770,8 @@
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
interconnect-names = "qup-core", "qup-config";
- dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
- <&gpi_dma1 1 2 QCOM_GPI_SPI>;
+ dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI 64>,
+ <&gpi_dma1 1 2 QCOM_GPI_SPI 64>;
dma-names = "tx", "rx";
status = "disabled";
};
@@ -1809,8 +1809,8 @@
"qup-memory";
power-domains = <&rpmhpd SC7280_CX>;
required-opps = <&rpmhpd_opp_low_svs>;
- dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
- <&gpi_dma1 1 3 QCOM_GPI_I2C>;
+ dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C 64>,
+ <&gpi_dma1 1 3 QCOM_GPI_I2C 64>;
dma-names = "tx", "rx";
status = "disabled";
};
@@ -1830,8 +1830,8 @@
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
interconnect-names = "qup-core", "qup-config";
- dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
- <&gpi_dma1 1 3 QCOM_GPI_SPI>;
+ dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI 64>,
+ <&gpi_dma1 1 3 QCOM_GPI_SPI 64>;
dma-names = "tx", "rx";
status = "disabled";
};
@@ -1869,8 +1869,8 @@
"qup-memory";
power-domains = <&rpmhpd SC7280_CX>;
required-opps = <&rpmhpd_opp_low_svs>;
- dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
- <&gpi_dma1 1 4 QCOM_GPI_I2C>;
+ dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C 64>,
+ <&gpi_dma1 1 4 QCOM_GPI_I2C 64>;
dma-names = "tx", "rx";
status = "disabled";
};
@@ -1890,8 +1890,8 @@
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
interconnect-names = "qup-core", "qup-config";
- dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
- <&gpi_dma1 1 4 QCOM_GPI_SPI>;
+ dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI 64>,
+ <&gpi_dma1 1 4 QCOM_GPI_SPI 64>;
dma-names = "tx", "rx";
status = "disabled";
};
@@ -1929,8 +1929,8 @@
"qup-memory";
power-domains = <&rpmhpd SC7280_CX>;
required-opps = <&rpmhpd_opp_low_svs>;
- dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
- <&gpi_dma1 1 5 QCOM_GPI_I2C>;
+ dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C 64>,
+ <&gpi_dma1 1 5 QCOM_GPI_I2C 64>;
dma-names = "tx", "rx";
status = "disabled";
};
@@ -1950,8 +1950,8 @@
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
interconnect-names = "qup-core", "qup-config";
- dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
- <&gpi_dma1 1 5 QCOM_GPI_SPI>;
+ dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI 64>,
+ <&gpi_dma1 1 5 QCOM_GPI_SPI 64>;
dma-names = "tx", "rx";
status = "disabled";
};
@@ -1989,8 +1989,8 @@
"qup-memory";
power-domains = <&rpmhpd SC7280_CX>;
required-opps = <&rpmhpd_opp_low_svs>;
- dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
- <&gpi_dma1 1 6 QCOM_GPI_I2C>;
+ dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C 64>,
+ <&gpi_dma1 1 6 QCOM_GPI_I2C 64>;
dma-names = "tx", "rx";
status = "disabled";
};
@@ -2010,8 +2010,8 @@
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
interconnect-names = "qup-core", "qup-config";
- dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
- <&gpi_dma1 1 6 QCOM_GPI_SPI>;
+ dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI 64>,
+ <&gpi_dma1 1 6 QCOM_GPI_SPI 64>;
dma-names = "tx", "rx";
status = "disabled";
};
@@ -2049,8 +2049,8 @@
"qup-memory";
power-domains = <&rpmhpd SC7280_CX>;
required-opps = <&rpmhpd_opp_low_svs>;
- dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
- <&gpi_dma1 1 7 QCOM_GPI_I2C>;
+ dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C 64>,
+ <&gpi_dma1 1 7 QCOM_GPI_I2C 64>;
dma-names = "tx", "rx";
status = "disabled";
};
@@ -2070,8 +2070,8 @@
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
interconnect-names = "qup-core", "qup-config";
- dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
- <&gpi_dma1 1 7 QCOM_GPI_SPI>;
+ dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI 64>,
+ <&gpi_dma1 1 7 QCOM_GPI_SPI 64>;
dma-names = "tx", "rx";
status = "disabled";
};
--
2.17.1

Next message: Jyothi Kumar Seerapu: "[PATCH v1 3/5] dmaengine: qcom: gpi: Add provision to support TRE size as the fourth argument of dma-cells property"
Previous message: Jyothi Kumar Seerapu: "[PATCH v1 1/5] dt-bindings: dmaengine: qcom: gpi: Add additional arg to dma-cell property"
In reply to: Rob Herring: "Re: [PATCH v1 1/5] dt-bindings: dmaengine: qcom: gpi: Add additional arg to dma-cell property"
Next in thread: Krzysztof Kozlowski: "Re: [PATCH v1 2/5] arm64: dts: qcom: Add support for configuring channel TRE size"
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]