Re: [PATCH V8 1/5] phy: freescale: fsl-samsung-hdmi: Replace register defines with macro

From: Adam Ford
Date: Tue Oct 15 2024 - 22:38:30 EST

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On Mon, Oct 7, 2024 at 11:39 AM Adam Ford <aford173@xxxxxxxxx> wrote:
>
> On Sat, Sep 14, 2024 at 6:28 AM Adam Ford <aford173@xxxxxxxxx> wrote:
> >
> > There are 47 registers defined as PHY_REG_xx were xx goes from 00 to
> > 47. Simplify this by replacing them all with a macro which is passed
> > the register number to return the proper register offset.
> >
> > Signed-off-by: Adam Ford <aford173@xxxxxxxxx>
> > Reviewed-by: Marco Felsch <m.felsch@xxxxxxxxxxxxxx>
> > Reviewed-by: Frieder Schrempf <frieder.schrempf@xxxxxxxxxx>
> > Tested-by: Frieder Schrempf <frieder.schrempf@xxxxxxxxxx>
> > Reviewed-by: Dominique Martinet <dominique.martinet@xxxxxxxxxxxxxxxxx>
> > Tested-by: Dominique Martinet <dominique.martinet@xxxxxxxxxxxxxxxxx>
>
> Gentile nudge on this series. RC2 is out, and I was hoping this
> might be merged to linux-next soon.

Vinod,

Is there anything you need from me to get this accepted? I thought I
addressed all your concerns and we have multiple r-b and t-b tags.

adam
>
> thanks
>
> adam
>
> > ---
> > V7: No change
> > V6: No change
> > ---
> > drivers/phy/freescale/phy-fsl-samsung-hdmi.c | 133 ++++++-------------
> > 1 file changed, 43 insertions(+), 90 deletions(-)
> >
> > diff --git a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c
> > index 9048cdc760c2..acea7008aefc 100644
> > --- a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c
> > +++ b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c
> > @@ -14,76 +14,29 @@
> > #include <linux/platform_device.h>
> > #include <linux/pm_runtime.h>
> >
> > -#define PHY_REG_00 0x00
> > -#define PHY_REG_01 0x04
> > -#define PHY_REG_02 0x08
> > -#define PHY_REG_08 0x20
> > -#define PHY_REG_09 0x24
> > -#define PHY_REG_10 0x28
> > -#define PHY_REG_11 0x2c
> > -
> > -#define PHY_REG_12 0x30
> > -#define REG12_CK_DIV_MASK GENMASK(5, 4)
> > -
> > -#define PHY_REG_13 0x34
> > -#define REG13_TG_CODE_LOW_MASK GENMASK(7, 0)
> > -
> > -#define PHY_REG_14 0x38
> > -#define REG14_TOL_MASK GENMASK(7, 4)
> > -#define REG14_RP_CODE_MASK GENMASK(3, 1)
> > -#define REG14_TG_CODE_HIGH_MASK GENMASK(0, 0)
> > -
> > -#define PHY_REG_15 0x3c
> > -#define PHY_REG_16 0x40
> > -#define PHY_REG_17 0x44
> > -#define PHY_REG_18 0x48
> > -#define PHY_REG_19 0x4c
> > -#define PHY_REG_20 0x50
> > -
> > -#define PHY_REG_21 0x54
> > -#define REG21_SEL_TX_CK_INV BIT(7)
> > -#define REG21_PMS_S_MASK GENMASK(3, 0)
> > -
> > -#define PHY_REG_22 0x58
> > -#define PHY_REG_23 0x5c
> > -#define PHY_REG_24 0x60
> > -#define PHY_REG_25 0x64
> > -#define PHY_REG_26 0x68
> > -#define PHY_REG_27 0x6c
> > -#define PHY_REG_28 0x70
> > -#define PHY_REG_29 0x74
> > -#define PHY_REG_30 0x78
> > -#define PHY_REG_31 0x7c
> > -#define PHY_REG_32 0x80
> > +#define PHY_REG(reg) (reg * 4)
> >
> > +#define REG12_CK_DIV_MASK GENMASK(5, 4)
> > +
> > +#define REG13_TG_CODE_LOW_MASK GENMASK(7, 0)
> > +
> > +#define REG14_TOL_MASK GENMASK(7, 4)
> > +#define REG14_RP_CODE_MASK GENMASK(3, 1)
> > +#define REG14_TG_CODE_HIGH_MASK GENMASK(0, 0)
> > +
> > +#define REG21_SEL_TX_CK_INV BIT(7)
> > +#define REG21_PMS_S_MASK GENMASK(3, 0)
> > /*
> > * REG33 does not match the ref manual. According to Sandor Yu from NXP,
> > * "There is a doc issue on the i.MX8MP latest RM"
> > * REG33 is being used per guidance from Sandor
> > */
> > +#define REG33_MODE_SET_DONE BIT(7)
> > +#define REG33_FIX_DA BIT(1)
> >
> > -#define PHY_REG_33 0x84
> > -#define REG33_MODE_SET_DONE BIT(7)
> > -#define REG33_FIX_DA BIT(1)
> > -
> > -#define PHY_REG_34 0x88
> > -#define REG34_PHY_READY BIT(7)
> > -#define REG34_PLL_LOCK BIT(6)
> > -#define REG34_PHY_CLK_READY BIT(5)
> > -
> > -#define PHY_REG_35 0x8c
> > -#define PHY_REG_36 0x90
> > -#define PHY_REG_37 0x94
> > -#define PHY_REG_38 0x98
> > -#define PHY_REG_39 0x9c
> > -#define PHY_REG_40 0xa0
> > -#define PHY_REG_41 0xa4
> > -#define PHY_REG_42 0xa8
> > -#define PHY_REG_43 0xac
> > -#define PHY_REG_44 0xb0
> > -#define PHY_REG_45 0xb4
> > -#define PHY_REG_46 0xb8
> > -#define PHY_REG_47 0xbc
> > +#define REG34_PHY_READY BIT(7)
> > +#define REG34_PLL_LOCK BIT(6)
> > +#define REG34_PHY_CLK_READY BIT(5)
> >
> > #define PHY_PLL_DIV_REGS_NUM 6
> >
> > @@ -369,29 +322,29 @@ struct reg_settings {
> > };
> >
> > static const struct reg_settings common_phy_cfg[] = {
> > - { PHY_REG_00, 0x00 }, { PHY_REG_01, 0xd1 },
> > - { PHY_REG_08, 0x4f }, { PHY_REG_09, 0x30 },
> > - { PHY_REG_10, 0x33 }, { PHY_REG_11, 0x65 },
> > + { PHY_REG(0), 0x00 }, { PHY_REG(1), 0xd1 },
> > + { PHY_REG(8), 0x4f }, { PHY_REG(9), 0x30 },
> > + { PHY_REG(10), 0x33 }, { PHY_REG(11), 0x65 },
> > /* REG12 pixclk specific */
> > /* REG13 pixclk specific */
> > /* REG14 pixclk specific */
> > - { PHY_REG_15, 0x80 }, { PHY_REG_16, 0x6c },
> > - { PHY_REG_17, 0xf2 }, { PHY_REG_18, 0x67 },
> > - { PHY_REG_19, 0x00 }, { PHY_REG_20, 0x10 },
> > + { PHY_REG(15), 0x80 }, { PHY_REG(16), 0x6c },
> > + { PHY_REG(17), 0xf2 }, { PHY_REG(18), 0x67 },
> > + { PHY_REG(19), 0x00 }, { PHY_REG(20), 0x10 },
> > /* REG21 pixclk specific */
> > - { PHY_REG_22, 0x30 }, { PHY_REG_23, 0x32 },
> > - { PHY_REG_24, 0x60 }, { PHY_REG_25, 0x8f },
> > - { PHY_REG_26, 0x00 }, { PHY_REG_27, 0x00 },
> > - { PHY_REG_28, 0x08 }, { PHY_REG_29, 0x00 },
> > - { PHY_REG_30, 0x00 }, { PHY_REG_31, 0x00 },
> > - { PHY_REG_32, 0x00 }, { PHY_REG_33, 0x80 },
> > - { PHY_REG_34, 0x00 }, { PHY_REG_35, 0x00 },
> > - { PHY_REG_36, 0x00 }, { PHY_REG_37, 0x00 },
> > - { PHY_REG_38, 0x00 }, { PHY_REG_39, 0x00 },
> > - { PHY_REG_40, 0x00 }, { PHY_REG_41, 0xe0 },
> > - { PHY_REG_42, 0x83 }, { PHY_REG_43, 0x0f },
> > - { PHY_REG_44, 0x3E }, { PHY_REG_45, 0xf8 },
> > - { PHY_REG_46, 0x00 }, { PHY_REG_47, 0x00 }
> > + { PHY_REG(22), 0x30 }, { PHY_REG(23), 0x32 },
> > + { PHY_REG(24), 0x60 }, { PHY_REG(25), 0x8f },
> > + { PHY_REG(26), 0x00 }, { PHY_REG(27), 0x00 },
> > + { PHY_REG(28), 0x08 }, { PHY_REG(29), 0x00 },
> > + { PHY_REG(30), 0x00 }, { PHY_REG(31), 0x00 },
> > + { PHY_REG(32), 0x00 }, { PHY_REG(33), 0x80 },
> > + { PHY_REG(34), 0x00 }, { PHY_REG(35), 0x00 },
> > + { PHY_REG(36), 0x00 }, { PHY_REG(37), 0x00 },
> > + { PHY_REG(38), 0x00 }, { PHY_REG(39), 0x00 },
> > + { PHY_REG(40), 0x00 }, { PHY_REG(41), 0xe0 },
> > + { PHY_REG(42), 0x83 }, { PHY_REG(43), 0x0f },
> > + { PHY_REG(44), 0x3E }, { PHY_REG(45), 0xf8 },
> > + { PHY_REG(46), 0x00 }, { PHY_REG(47), 0x00 }
> > };
> >
> > struct fsl_samsung_hdmi_phy {
> > @@ -442,7 +395,7 @@ fsl_samsung_hdmi_phy_configure_pixclk(struct fsl_samsung_hdmi_phy *phy,
> > }
> >
> > writeb(REG21_SEL_TX_CK_INV | FIELD_PREP(REG21_PMS_S_MASK, div),
> > - phy->regs + PHY_REG_21);
> > + phy->regs + PHY_REG(21));
> > }
> >
> > static void
> > @@ -469,7 +422,7 @@ fsl_samsung_hdmi_phy_configure_pll_lock_det(struct fsl_samsung_hdmi_phy *phy,
> > break;
> > }
> >
> > - writeb(FIELD_PREP(REG12_CK_DIV_MASK, ilog2(div)), phy->regs + PHY_REG_12);
> > + writeb(FIELD_PREP(REG12_CK_DIV_MASK, ilog2(div)), phy->regs + PHY_REG(12));
> >
> > /*
> > * Calculation for the frequency lock detector target code (fld_tg_code)
> > @@ -489,11 +442,11 @@ fsl_samsung_hdmi_phy_configure_pll_lock_det(struct fsl_samsung_hdmi_phy *phy,
> >
> > /* FLD_TOL and FLD_RP_CODE taken from downstream driver */
> > writeb(FIELD_PREP(REG13_TG_CODE_LOW_MASK, fld_tg_code),
> > - phy->regs + PHY_REG_13);
> > + phy->regs + PHY_REG(13));
> > writeb(FIELD_PREP(REG14_TOL_MASK, 2) |
> > FIELD_PREP(REG14_RP_CODE_MASK, 2) |
> > FIELD_PREP(REG14_TG_CODE_HIGH_MASK, fld_tg_code >> 8),
> > - phy->regs + PHY_REG_14);
> > + phy->regs + PHY_REG(14));
> > }
> >
> > static int fsl_samsung_hdmi_phy_configure(struct fsl_samsung_hdmi_phy *phy,
> > @@ -503,7 +456,7 @@ static int fsl_samsung_hdmi_phy_configure(struct fsl_samsung_hdmi_phy *phy,
> > u8 val;
> >
> > /* HDMI PHY init */
> > - writeb(REG33_FIX_DA, phy->regs + PHY_REG_33);
> > + writeb(REG33_FIX_DA, phy->regs + PHY_REG(33));
> >
> > /* common PHY registers */
> > for (i = 0; i < ARRAY_SIZE(common_phy_cfg); i++)
> > @@ -511,14 +464,14 @@ static int fsl_samsung_hdmi_phy_configure(struct fsl_samsung_hdmi_phy *phy,
> >
> > /* set individual PLL registers PHY_REG2 ... PHY_REG7 */
> > for (i = 0; i < PHY_PLL_DIV_REGS_NUM; i++)
> > - writeb(cfg->pll_div_regs[i], phy->regs + PHY_REG_02 + i * 4);
> > + writeb(cfg->pll_div_regs[i], phy->regs + PHY_REG(2) + i * 4);
> >
> > fsl_samsung_hdmi_phy_configure_pixclk(phy, cfg);
> > fsl_samsung_hdmi_phy_configure_pll_lock_det(phy, cfg);
> >
> > - writeb(REG33_FIX_DA | REG33_MODE_SET_DONE, phy->regs + PHY_REG_33);
> > + writeb(REG33_FIX_DA | REG33_MODE_SET_DONE, phy->regs + PHY_REG(33));
> >
> > - ret = readb_poll_timeout(phy->regs + PHY_REG_34, val,
> > + ret = readb_poll_timeout(phy->regs + PHY_REG(34), val,
> > val & REG34_PLL_LOCK, 50, 20000);
> > if (ret)
> > dev_err(phy->dev, "PLL failed to lock\n");
> > --
> > 2.43.0
> >

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