On Thu, Oct 17, 2024 at 10:40:36AM -0600, Keith Busch wrote:
On Wed, Oct 16, 2024 at 09:31:08PM +0000, Abhishek Bapat wrote:Yes. Plus the virt boundary for PRPs, and for non-PCIe tranfers
max_hw_sectors based on DMA optimized limitation") introduced aThere are other limits that can constrain transfer sizes below the
limitation on the value of max_hw_sectors_kb, restricting it to 128KiB
(MDTS = 5). This restricion was implemented to mitigate lockups
encountered in high-core count AMD servers.
device's MDTS. For example, the driver can only preallocate so much
space for DMA and SGL descriptors, so 8MB is the current max transfer
sizes the driver can support, and a device's MDTS can be much bigger
than that.
there's also plenty of other hardware limits due to e.g. the FC HBA
and the RDMA HCA limit. There's also been some talk of a new PCIe
SGL variant with hard limits.
So I agree that exposting limits on I/O would be very useful, but it's
also kinda non-trivial.