Re: [PATCH v3 1/8] media: dt-bindings: media: camss: Add qcom,sc7280-camss binding

[Vikram Sharma]

Hi Krzysztof,

Thanks for your review. I will address the alignment issue as per DTS 
coding style and will submit v4 for review.

Thanks,
Vikram

On 10/11/2024 8:19 PM, Krzysztof Kozlowski wrote:
> On Fri, Oct 11, 2024 at 07:39:25PM +0530, Vikram Sharma wrote:
> > @@ -0,0 +1,440 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +
> Drop blank line (that's a new finding, I would not complain except that
> I expect new version, see further).
>
> > +    soc {
> > +        #address-cells = <2>;
> > +        #size-cells = <2>;
> > +
> > +        camss: camss@acaf000 {
> > +            compatible = "qcom,sc7280-camss";
> > +
> > +            clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
> > +                <&clock_camcc CAM_CC_IFE_0_CSID_CLK>,
> Alignment did not improve. Please carefully read DTS coding style.
>
> > +                <&clock_camcc CAM_CC_IFE_1_CSID_CLK>,
> > +                <&clock_camcc CAM_CC_IFE_2_CSID_CLK>,
> > +                <&clock_camcc CAM_CC_IFE_LITE_0_CSID_CLK>,
> > +                <&clock_camcc CAM_CC_IFE_LITE_1_CSID_CLK>,
> > +                <&clock_camcc CAM_CC_CSIPHY0_CLK>,
> > +                <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>,
> > +                <&clock_camcc CAM_CC_CSIPHY1_CLK>,
> > +                <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>,
> > +                <&clock_camcc CAM_CC_CSIPHY2_CLK>,
> > +                <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>,
> > +                <&clock_camcc CAM_CC_CSIPHY3_CLK>,
> > +                <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>,
> > +                <&clock_camcc CAM_CC_CSIPHY4_CLK>,
> > +                <&clock_camcc CAM_CC_CSI4PHYTIMER_CLK>,
> > +                <&gcc GCC_CAMERA_AHB_CLK>,
> > +                <&gcc GCC_CAMERA_HF_AXI_CLK>,
> > +                <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
> > +                <&clock_camcc CAM_CC_IFE_0_AXI_CLK>,
> > +                <&clock_camcc CAM_CC_IFE_0_CLK>,
> > +                <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
> > +                <&clock_camcc CAM_CC_IFE_1_AXI_CLK>,
> > +                <&clock_camcc CAM_CC_IFE_1_CLK>,
> > +                <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
> > +                <&clock_camcc CAM_CC_IFE_2_AXI_CLK>,
> > +                <&clock_camcc CAM_CC_IFE_2_CLK>,
> > +                <&clock_camcc CAM_CC_IFE_2_CPHY_RX_CLK>,
> > +                <&clock_camcc CAM_CC_IFE_LITE_0_CLK>,
> > +                <&clock_camcc CAM_CC_IFE_LITE_0_CPHY_RX_CLK>,
> > +                <&clock_camcc CAM_CC_IFE_LITE_1_CLK>,
> > +                <&clock_camcc CAM_CC_IFE_LITE_1_CPHY_RX_CLK>;
> > +
> > +            clock-names = "camnoc_axi",
> > +                "csi0",
> Alignment did not improve. Please carefully read DTS coding style.
>
> > +                "csi1",
> > +                "csi2",
> > +                "csi3",
> > +                "csi4",
> > +                "csiphy0",
> > +                "csiphy0_timer",
> > +                "csiphy1",
> > +                "csiphy1_timer",
> > +                "csiphy2",
> > +                "csiphy2_timer",
> > +                "csiphy3",
> > +                "csiphy3_timer",
> > +                "csiphy4",
> > +                "csiphy4_timer",
> > +                "gcc_camera_ahb",
> > +                "gcc_camera_axi",
> > +                "soc_ahb",
> > +                "vfe0_axi",
> > +                "vfe0",
> > +                "vfe0_cphy_rx",
> > +                "vfe1_axi",
> > +                "vfe1",
> > +                "vfe1_cphy_rx",
> > +                "vfe2_axi",
> > +                "vfe2",
> > +                "vfe2_cphy_rx",
> > +                "vfe0_lite",
> > +                "vfe0_lite_cphy_rx",
> > +                "vfe1_lite",
> > +                "vfe1_lite_cphy_rx";
> > +
> > +            interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_CAMERA_CFG 0>,
> > +                <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>;
> Alignment did not improve. Please carefully read DTS coding style.
>
> > +
> > +            interconnect-names = "ahb", "hf_0";
> > +
> > +            interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
> > +                <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
> Alignment did not improve. Please carefully read DTS coding style.
>
> > +                <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>,
> > +                <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
> > +                <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
> > +                <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
> > +                <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
> > +                <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
> > +                <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
> > +                <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
> > +                <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
> > +                <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
> > +                <GIC_SPI 641 IRQ_TYPE_EDGE_RISING>,
> > +                <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
> > +                <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>;
> > +
> > +            interrupt-names = "csid0",
> > +                "csid1",
> > +                "csid2",
> > +                "csid_lite0",
> Alignment did not improve. Please carefully read DTS coding style.
>
> > +                "csid_lite1",
> > +                "csiphy0",
> > +                "csiphy1",
> > +                "csiphy2",
> > +                "csiphy3",
> > +                "csiphy4",
> > +                "vfe0",
> > +                "vfe1",
> > +                "vfe2",
> > +                "vfe_lite0",
> > +                "vfe_lite1";
> > +
> > +            iommus = <&apps_smmu 0x800 0x4e0>;
> > +
> > +            power-domains = <&camcc CAM_CC_IFE_0_GDSC>,
> > +                <&camcc CAM_CC_IFE_1_GDSC>,
> Alignment did not improve. Please carefully read DTS coding style.
>
> > +                <&camcc CAM_CC_IFE_2_GDSC>,
> > +                <&camcc CAM_CC_TITAN_TOP_GDSC>;
> > +
> > +            power-domains-names = "ife0", "ife1", "ife2", "top";
> > +
> > +            reg = <0x0 0x0acb3000 0x0 0x1000>,
> > +                <0x0 0x0acba000 0x0 0x1000>,
> > +                <0x0 0x0acc1000 0x0 0x1000>,
> Alignment did not improve. Please carefully read DTS coding style.
>
> > +                <0x0 0x0acc8000 0x0 0x1000>,
> > +                <0x0 0x0accf000 0x0 0x1000>,
> > +                <0x0 0x0ace0000 0x0 0x2000>,
> > +                <0x0 0x0ace2000 0x0 0x2000>,
> > +                <0x0 0x0ace4000 0x0 0x2000>,
> > +                <0x0 0x0ace6000 0x0 0x2000>,
> > +                <0x0 0x0ace8000 0x0 0x2000>,
> > +                <0x0 0x0acaf000 0x0 0x4000>,
> > +                <0x0 0x0acb6000 0x0 0x4000>,
> > +                <0x0 0x0acbd000 0x0 0x4000>,
> > +                <0x0 0x0acc4000 0x0 0x4000>,
> > +                <0x0 0x0accb000 0x0 0x4000>;
> > +
> > +            reg-names = "csid0",
> > +                "csid1",
> > +                "csid2",
> > +                "csid_lite0",
> Alignment did not improve. Please carefully read DTS coding style.
>
> > +                "csid_lite1",
> > +                "csiphy0",
> > +                "csiphy1",
> > +                "csiphy2",
> Best regards,
> Krzysztof