Re: [PATCH] clk: qcom: gcc-qcs404: fix initial rate of GPLL3

[Bryan O'Donoghue]

On 22/10/2024 10:45, Gabor Juhos wrote:
> The comment before the config of the GPLL3 PLL says that the
> PLL should run at 930 MHz. In contrary to this, calculating
> the frequency from the current configuration values by using
> 19.2 MHz as input frequency defined in 'qcs404.dtsi', it gives
> 921.6 MHz:
>
>    $ xo=19200000; l=48; alpha=0x0; alpha_hi=0x0
>    $ echo "$xo * ($((l)) + $(((alpha_hi << 32 | alpha) >> 8)) / 2^32)" | bc -l
>    921600000.00000000000000000000
>
> Set 'alpha_hi' in the configuration to a value used in downstream
> kernels [1][2] in order to get the correct output rate:
>
>    $ xo=19200000; l=48; alpha=0x0; alpha_hi=0x70
>    $ echo "$xo * ($((l)) + $(((alpha_hi << 32 | alpha) >> 8)) / 2^32)" | bc -l
>    930000000.00000000000000000000
>
> The change is based on static code analysis, compile tested only.
>
> [1] https://git.codelinaro.org/clo/la/kernel/msm-5.4/-/blob/kernel.lnx.5.4.r56-rel/drivers/clk/qcom/gcc-qcs404.c?ref_type=heads#L335
> [2} https://git.codelinaro.org/clo/la/kernel/msm-5.15/-/blob/kernel.lnx.5.15.r49-rel/drivers/clk/qcom/gcc-qcs404.c?ref_type=heads#L127
>
> Cc: stable@xxxxxxxxxxxxxxx
> Fixes: 652f1813c113 ("clk: qcom: gcc: Add global clock controller driver for QCS404")
> Signed-off-by: Gabor Juhos <j4g8y7@xxxxxxxxx>
It should be possible to test / verify this change with debugcc on qcs404

https://github.com/linux-msm/debugcc/blob/master/qcs404.c

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