On Wed, Oct 16, 2024 at 08:04:10PM -0700, Qiang Yu wrote:Get confirmation from HW team. 1.21.0 is Qcom IP rev of sc8280xp,
On SC8280X family SoC, PCIe controllers are connected to SMMUv3, henceThe sc8280xp PCIe devicetree nodes do not specify an 'iommu-map' so the
they don't need the config_sid() callback in ops_1_9_0 struct. Fix it by
introducing a new ops struct, namely ops_1_21_0 which is same as ops_1_9_0
without config_sid() callback so that BDF2SID mapping won't be configured
during init.
config_sid() callback is effectively a no-op. Please rephrase this so
that it becomes obvious that this is a clean up rather than fix.
Fixes: 70574511f3fc ("PCI: qcom: Add support for SC8280XP")And drop the Fixes tag.
Signed-off-by: Qiang Yu <quic_qianyu@xxxxxxxxxxx>Is this the actual IP revision on sc8280xp (and not just the revision
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
---
drivers/pci/controller/dwc/pcie-qcom.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 88a98be930e3..468bd4242e61 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -1367,6 +1367,16 @@ static const struct qcom_pcie_ops ops_2_9_0 = {
.ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
};
+/* Qcom IP rev.: 1.21.0 */
used on x1e80100)?
Please also provide the Synopsis IP rev like the other configs do.
+static const struct qcom_pcie_ops ops_1_21_0 = {And try to keep these structs sorted by revision. At least put this one
+ .get_resources = qcom_pcie_get_resources_2_7_0,
+ .init = qcom_pcie_init_2_7_0,
+ .post_init = qcom_pcie_post_init_2_7_0,
+ .host_post_init = qcom_pcie_host_post_init_2_7_0,
+ .deinit = qcom_pcie_deinit_2_7_0,
+ .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
+};
+
static const struct qcom_pcie_cfg cfg_1_0_0 = {
.ops = &ops_1_0_0,
};
after ops_1_9_0.
Johan