Re: [PATCH v3 12/15] drm/bridge: Add ITE IT6263 LVDS to HDMI converter

[Liu Ying]

On 10/24/2024, Biju Das wrote:
> Hi Liu Ying,

Hi Biju,

> 
>> -----Original Message-----
>> From: Liu Ying <victor.liu@xxxxxxx>
>> Sent: Monday, October 21, 2024 7:45 AM
>> Subject: [PATCH v3 12/15] drm/bridge: Add ITE IT6263 LVDS to HDMI converter
>>
>> Add basic HDMI video output support. Currently, only RGB888 output pixel format is supported.  At the
>> LVDS input side, the driver supports single LVDS link and dual LVDS links with "jeida-24" LVDS
>> mapping.
>>
>> Product link:
>> https://www.ite.com.tw/en/product/cate1/IT6263
> 
> Just a question,
> 
> What is the maximum single link and dual link modes you have tested?

With single LVDS link on i.MX8MP EVK, the highest pixel clock rate I
tested is 74.25MHz(1280x720@60).  i.MX8MP LVDS Display Bridge(LDB)
supports the highest 80MHz pixel clock rate with single LVDS link.

With single LVDS link on i.MX8qxp MEK, the highest pixel clock rate I
tested is 148.5MHz(1920x1080@60).  i.MX8qxp LDB supports the highest
150MHz pixel clock rate with single LVDS link.

With dual LVDS links on both i.MX8MP EVK and i.MX8qxp MEK, the highest
pixel clock rate I tested is 148.5MHz(1920x1080@60).

> 
> On Renesas SMARC RZ/G3E platform I have tested with this patch set,
> 
> Dual link :1080p@60
> 
> and
> 
> Single link:720p@60
> 
> For single link > 720p@60, sometimes I get message
> "it6263 7-004c: failed to wait for video stable"

I don't see this with i.MX8MP EVK and i.MX8qxp MEK.

> 
> From SoC side, it can support max dot clock of 87MHz for single link.
> 
> So just wondering other than reject modes greater than 87MHz from SOC
> side, do we need to limit any thing on bridge device for single link Case?

Since IT6263 works with 1920x1080@60(148.5MHz pixel clock rate) on
i.MX8qxp MEK by using single LVDS link, I'm currently fine with
the existing clock rate validation against the maximal 150MHz pixel
clock rate.

> 
> Cheers,
> Biju

-- 
Regards,
Liu Ying