On Thu, Oct 31, 2024 at 04:12:37PM +0100, Heiko Schocher wrote:[...]
Add support for the i.MX8MP based aristainetos3 boards from ABB.
The board uses a ABB specific SoM from ADLink, based on NXP
i.MX8MP SoC. The SoM is used on 3 different carrier boards,
with small differences.
Signed-off-by: Heiko Schocher <hs@xxxxxxx>
---
[...]diff --git a/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3a-som-v1.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3a-som-v1.dtsi
new file mode 100644
index 000000000000..ced35e1d72b7
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3a-som-v1.dtsi
+ pcie0_refclk: pcie0-refclk {
Can we name the node clock-xxx?
+ /* SX1509(0) U2605 */
+ gpio6: pinctrl@3f {
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ compatible = "semtech,sx1509q";
+ reg = <0x3f>;
+
+ semtech,probe-reset;
+ gpio-controller;
+ interrupt-controller;
+
+ interrupt-parent = <&gpio1>;
+ interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
+ };
+
+ /* SX1509(1) U2606 */
+ gpio7: pinctrl@70 {
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ compatible = "semtech,sx1509q";
+ reg = <0x70>;
+
+ semtech,probe-reset;
+ gpio-controller;
+ interrupt-controller;
+
+ interrupt-parent = <&gpio4>;
+ interrupts = <19 IRQ_TYPE_EDGE_FALLING>;
+
+ gpio6-cfg {
+ pins = "gpio6";
+ output-high;
+ };
+
+ gpio7-cfg {
+ pins = "gpio7";
+ output-high;
+ };
+ };
+
+ /* RTC U2607 */
+ rtc0: rtc@51 {
I2C slave nodes should be sorted in addresses.
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ #clock-cells = <0>;
+ };
+};
+
+&irqsteer_hdmi {
+ status = "okay";
+};
+
+&lcdif1 {
+ status = "disabled";
+};
+
+&lcdif2 {
+ status = "disabled";
+};
+
+/* HDMI */
+&lcdif3 {
+ status = "okay";
+
Unneeded newline.