Re: [PATCH 3/7] clk: qcom: clk-alpha-pll: Add support for controlling Taycan PLLs

[Taniya Das]

On 10/23/2024 9:18 AM, Bjorn Andersson wrote:
> On Mon, Oct 21, 2024 at 04:03:55PM GMT, Melody Olvera wrote:
> > From: Taniya Das <quic_tdas@xxxxxxxxxxx>
> >
> > Update the clock ops for Taycan PLL, add the register offsets for
> > supporting the PLL.
>
> Subject and patch says "Add" so why does it say "Update" here?

Will fix in the next patch.

> > Signed-off-by: Taniya Das <quic_tdas@xxxxxxxxxxx>
> > Signed-off-by: Melody Olvera <quic_molvera@xxxxxxxxxxx>
> > ---
> >   drivers/clk/qcom/clk-alpha-pll.c | 14 ++++++++++++++
> >   drivers/clk/qcom/clk-alpha-pll.h |  7 +++++++
> >   2 files changed, 21 insertions(+)
> >
> > diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
> > index be9bee6ab65f..57a15ac7b052 100644
> > --- a/drivers/clk/qcom/clk-alpha-pll.c
> > +++ b/drivers/clk/qcom/clk-alpha-pll.c
> > @@ -267,6 +267,20 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
> >   		[PLL_OFF_OPMODE] = 0x30,
> >   		[PLL_OFF_STATUS] = 0x3c,
> >   	},
> > +	[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU] = {
>
> The other entries in this array are following the order of the enum, how
> come this is different?

Sure, will align the order.

> Regards,
> Bjorn
>
> > +		[PLL_OFF_OPMODE] = 0x04,
> > +		[PLL_OFF_STATE] = 0x08,
> > +		[PLL_OFF_STATUS] = 0x0c,
> > +		[PLL_OFF_L_VAL] = 0x10,
> > +		[PLL_OFF_ALPHA_VAL] = 0x14,
> > +		[PLL_OFF_USER_CTL] = 0x18,
> > +		[PLL_OFF_USER_CTL_U] = 0x1c,
> > +		[PLL_OFF_CONFIG_CTL] = 0x20,
> > +		[PLL_OFF_CONFIG_CTL_U] = 0x24,
> > +		[PLL_OFF_CONFIG_CTL_U1] = 0x28,
> > +		[PLL_OFF_TEST_CTL] = 0x2c,
> > +		[PLL_OFF_TEST_CTL_U] = 0x30,
> > +	},
> >   };
> >   EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
> >   
> > diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
> > index 55eca04b23a1..5ba06d9ba77e 100644
> > --- a/drivers/clk/qcom/clk-alpha-pll.h
> > +++ b/drivers/clk/qcom/clk-alpha-pll.h
> > @@ -27,6 +27,7 @@ enum {
> >   	CLK_ALPHA_PLL_TYPE_ZONDA_OLE,
> >   	CLK_ALPHA_PLL_TYPE_LUCID_EVO,
> >   	CLK_ALPHA_PLL_TYPE_LUCID_OLE,
> > +	CLK_ALPHA_PLL_TYPE_TAYCAN_ELU,
> >   	CLK_ALPHA_PLL_TYPE_RIVIAN_EVO,
> >   	CLK_ALPHA_PLL_TYPE_DEFAULT_EVO,
> >   	CLK_ALPHA_PLL_TYPE_BRAMMO_EVO,
> > @@ -184,12 +185,15 @@ extern const struct clk_ops clk_alpha_pll_zonda_ops;
> >   #define clk_alpha_pll_zonda_ole_ops clk_alpha_pll_zonda_ops
> >   
> >   extern const struct clk_ops clk_alpha_pll_lucid_evo_ops;
> > +#define clk_alpha_pll_taycan_elu_ops clk_alpha_pll_lucid_evo_ops
> >   extern const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops;
> >   #define clk_alpha_pll_reset_lucid_ole_ops clk_alpha_pll_reset_lucid_evo_ops
> >   extern const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops;
> >   #define clk_alpha_pll_fixed_lucid_ole_ops clk_alpha_pll_fixed_lucid_evo_ops
> > +#define clk_alpha_pll_fixed_taycan_elu_ops clk_alpha_pll_fixed_lucid_evo_ops
> >   extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops;
> >   #define clk_alpha_pll_postdiv_lucid_ole_ops clk_alpha_pll_postdiv_lucid_evo_ops
> > +#define clk_alpha_pll_postdiv_taycan_elu_ops clk_alpha_pll_postdiv_lucid_evo_ops
> >   
> >   extern const struct clk_ops clk_alpha_pll_rivian_evo_ops;
> >   #define clk_alpha_pll_postdiv_rivian_evo_ops clk_alpha_pll_postdiv_fabia_ops
> > @@ -217,6 +221,9 @@ void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regma
> >   				 const struct alpha_pll_config *config);
> >   void clk_lucid_ole_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
> >   				 const struct alpha_pll_config *config);
> > +#define clk_taycan_elu_pll_configure(pll, regmap, config) \
> > +	clk_lucid_evo_pll_configure(pll, regmap, config)
> > +
> >   void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
> >   				  const struct alpha_pll_config *config);
> >   void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
> > --
> > 2.46.1

--
Thanks & Regards,
Taniya Das.