Re: [PATCH net-next] eth: fbnic: Add PCIe hardware statistics

[Leon Romanovsky]

On Wed, Nov 06, 2024 at 03:17:38PM -0600, Bjorn Helgaas wrote:
> On Wed, Nov 06, 2024 at 07:50:54PM +0200, Leon Romanovsky wrote:
> > On Wed, Nov 06, 2024 at 11:12:57AM -0600, Bjorn Helgaas wrote:
> > > On Wed, Nov 06, 2024 at 02:22:51PM +0200, Leon Romanovsky wrote:
> > > > On Tue, Nov 05, 2024 at 04:26:25PM -0800, Sanman Pradhan wrote:
> > > > > Add PCIe hardware statistics support to the fbnic driver. These stats
> > > > > provide insight into PCIe transaction performance and error conditions,
> > > > > including, read/write and completion TLP counts and DWORD counts and
> > > > > debug counters for tag, completion credit and NP credit exhaustion
> > > > > 
> > > > > The stats are exposed via ethtool and can be used to monitor PCIe
> > > > > performance and debug PCIe issues.
> > > > 
> > > > And how does PCIe statistics belong to ethtool?
> > > > 
> > > > This PCIe statistics to debug PCIe errors and arguably should be part of
> > > > PCI core and not hidden in netdev tool.
> > > 
> > > How would this be done in the PCI core?  As far as I can tell, all
> > > these registers are device-specific and live in some device BAR.
> > 
> > I would expect some sysfs file/directory exposed through PCI core.
> > That sysfs needs to be connected to the relevant device through
> > callback, like we are doing with .sriov_configure(). So every PCI
> > device will be able to expose statistics without relation to netdev.
> > 
> > That interface should provide read access and write access with zero
> > value to reset the counter/counters.
> 
> Seems plausible.  We do already have something sort of similar with
> aer_stats_attrs[].  I don't think there's a way to reset them though,

Our HW supports reset of PCIe counters.

> and they're just all thrown in the top-level device directory, which
> probably isn't scalable.

This is why directory is probably the best solution.

Thanks

> 
> Bjorn