Re: [PATCH v6 0/2] PCI: microchip: support using either instance 1 or 2

[Bjorn Helgaas]

On Thu, Nov 07, 2024 at 10:59:33AM +0000, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
> 
> The current driver and binding for PolarFire SoC's PCI controller assume
> that the root port instance in use is instance 1. The second reg
> property constitutes the region encompassing both "control" and "bridge"
> registers for both instances. In the driver, a fixed offset is applied to
> find the base addresses for instance 1's "control" and "bridge"
> registers. The BeagleV Fire uses root port instance 2, so something must
> be done so that software can differentiate. This series splits the
> second reg property in two, with dedicated "control" and "bridge"
> entries so that either instance can be used.
> 
> Cheers,
> Conor.
> 
> v6:
> - rework commit messages to use Bjorn's preferred "root port" and "root
>   complex" wording
> 
> v5:
> - rebase on top of 6.11-rc1, which brought about a lot of driver change
>   due to the plda common driver creation - although little actually
>   changed in terms of the lines edited in this patch.
> 
> v4:
> - fix a cocci warning reported off list about an inconsistent variable
>   used between IS_ERR() and PTR_ERR() calls.
> 
> v3:
> - rename a variable in probe s/axi/apb/
> 
> v2:
> - try the new reg format before the old one to avoid warnings in the
>   good case
> - reword $subject for 2/2
> 
> CC: Daire McNamara <daire.mcnamara@xxxxxxxxxxxxx>
> CC: Lorenzo Pieralisi <lpieralisi@xxxxxxxxxx>
> CC: Krzysztof Wilczyński <kw@xxxxxxxxx>
> CC: Rob Herring <robh@xxxxxxxxxx>
> CC: Bjorn Helgaas <bhelgaas@xxxxxxxxxx>
> CC: Krzysztof Kozlowski <krzk+dt@xxxxxxxxxx>
> CC: Conor Dooley <conor+dt@xxxxxxxxxx>
> CC: linux-pci@xxxxxxxxxxxxxxx
> CC: devicetree@xxxxxxxxxxxxxxx
> CC: linux-kernel@xxxxxxxxxxxxxxx
> CC: linux-riscv@xxxxxxxxxxxxxxxxxxx
> 
> Conor Dooley (2):
>   dt-bindings: PCI: microchip,pcie-host: fix reg properties
>   PCI: microchip: rework reg region handing to support using either root
>     port 1 or 2
> 
>  .../bindings/pci/microchip,pcie-host.yaml     |  11 +-
>  .../pci/plda,xpressrich3-axi-common.yaml      |  14 ++-
>  .../bindings/pci/starfive,jh7110-pcie.yaml    |   7 ++
>  .../pci/controller/plda/pcie-microchip-host.c | 116 +++++++++---------
>  4 files changed, 87 insertions(+), 61 deletions(-)

Thanks!  The patches themselves are unchanged between v5 and v6.  I
replaced the v5 patches on pci/controller/microchip with these.

I also capitalized "Root Port" and "Root Complex" to give a hint that
they are proper nouns defined by the PCIe spec.