Re: [RESEND PATCH] clk: socfpga: arria10: Optimize local variables in clk_pll_recalc_rate()

[Dinh Nguyen]

On 10/26/24 10:53, Thorsten Blum wrote:
> Since readl() returns a u32, the local variable reg can also have the
> data type u32. Furthermore, divf and divq are derived from reg and can
> also be a u32.
>
> Since do_div() casts the divisor to u32 anyway, changing the data type
> of divq to u32 also removes the following Coccinelle/coccicheck warning
> reported by do_div.cocci:
>
>    WARNING: do_div() does a 64-by-32 division, please consider using div64_ul instead
>
> Compile-tested only.
>
> Signed-off-by: Thorsten Blum <thorsten.blum@xxxxxxxxx>
> ---
>   drivers/clk/socfpga/clk-pll-a10.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)

Applied, thanks!

Dinh