On Mon, Nov 11, 2024 at 01:59:37PM +0800, Chen Wang wrote:Got, thanks.
From: Chen Wang <unicorn_wang@xxxxxxxxxxx>Don't need '|+'
Add binding for Sophgo SG2042 PCIe host controller.
Signed-off-by: Chen Wang <unicorn_wang@xxxxxxxxxxx>
---
.../bindings/pci/sophgo,sg2042-pcie-host.yaml | 88 +++++++++++++++++++
1 file changed, 88 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml
diff --git a/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml b/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml
new file mode 100644
index 000000000000..d4d2232f354f
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml
@@ -0,0 +1,88 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/sophgo,sg2042-pcie-host.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo SG2042 PCIe Host (Cadence PCIe Wrapper)
+
+description: |+
Got, thanks.
+ Sophgo SG2042 PCIe host controller is based on the Cadence PCIe core.That's clear from the $ref. No need to say that in prose.
+ It shares common features with the PCIe core and inherits common properties
+ defined in Documentation/devicetree/bindings/pci/cdns-pcie-host.yaml.
Let me give you some background info.
+Please describe what you need to access.
+maintainers:
+ - Chen Wang <unicorn_wang@xxxxxxxxxxx>
+
+properties:
+ compatible:
+ const: sophgo,sg2042-pcie-host
+
+ reg:
+ maxItems: 2
+
+ reg-names:
+ items:
+ - const: reg
+ - const: cfg
+
+ sophgo,syscon-pcie-ctrl:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: Phandle to the SYSCON entry
+Is this an index or related to the syscon? Nak for the former, use
+ sophgo,link-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Cadence IP link ID.
linux,pci-domain. For the latter, add an arg to sophgo,syscon-pcie-ctrl.
I will check it out, thanks.+Wouldn't 'msi-parent' work for this purpose?
+ sophgo,internal-msi:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: Identifies whether the PCIE node uses internal MSI controller.
Got.
+ranges is already required in the common schemas.
+ vendor-id:
+ const: 0x1f1c
+
+ device-id:
+ const: 0x2042
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-names:
+ const: msi
+
+allOf:
+ - $ref: cdns-pcie-host.yaml#
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - sophgo,syscon-pcie-ctrl
+ - sophgo,link-id
+ - vendor-id
+ - device-id
+ - ranges
+
+additionalProperties: true
+
+examples:
+ - |
+ pcie@62000000 {
+ compatible = "sophgo,sg2042-pcie-host";
+ device_type = "pci";
+ reg = <0x62000000 0x00800000>,
+ <0x48000000 0x00001000>;
+ reg-names = "reg", "cfg";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000>,
+ <0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>;
+ bus-range = <0x80 0xbf>;
+ vendor-id = <0x1f1c>;
+ device-id = <0x2042>;
+ cdns,no-bar-match-nbits = <48>;
+ sophgo,link-id = <0>;
+ sophgo,syscon-pcie-ctrl = <&cdns_pcie1_ctrl>;
+ sophgo,internal-msi;
+ interrupt-parent = <&intc>;
+ };
--
2.34.1