[PATCH 1/2] dt-bindings: iio: frequency: Add ADF4382

[Ciprian Hegbeli]

The ADF4382A is a high performance, ultralow jitter, Frac-N PLL
with integrated VCO ideally suited for LO generation for 5G applications
or data converter clock applications. The high performance
PLL has a figure of merit of -239 dBc/Hz, low 1/f Noise and
high PFD frequency of 625MHz in integer mode that can achieve
ultralow in-band noise and integrated jitter. The ADF4382A can
generate frequencies in a fundamental octave range of 11.5 GHz to
21 GHz, thereby eliminating the need for sub-harmonic filters. The
divide by 2 and 4 output dividers on the part allow frequencies to
be generated from 5.75GHz to 10.5GHz and 2.875GHz to 5.25GHz
respectively.

Signed-off-by: Ciprian Hegbeli <ciprian.hegbeli@xxxxxxxxxx>
---
 .../bindings/iio/frequency/adi,adf4382.yaml   | 141 ++++++++++++++++++
 1 file changed, 141 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/iio/frequency/adi,adf4382.yaml

diff --git a/Documentation/devicetree/bindings/iio/frequency/adi,adf4382.yaml b/Documentation/devicetree/bindings/iio/frequency/adi,adf4382.yaml
new file mode 100644
index 000000000000..44a29ac7a2e8
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/frequency/adi,adf4382.yaml
@@ -0,0 +1,141 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/frequency/adi,adf4382.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ADF4382 Microwave Wideband Synthesizer with Integrated VCO
+
+maintainers:
+  - Antoniu Miclaus <antoniu.miclaus@xxxxxxxxxx>
+  - Ciprian Hegbeli <ciprian.hegbeli@xxxxxxxxxx>
+
+description: The ADF4382 is a high performance, ultralow jitter, Frac-N PLL with
+   integrated VCO ideally suited for LO generation for 5G applications
+   or data converter clock applications.
+
+   https://www.analog.com/en/products/adf4382a.html
+
+properties:
+  compatible:
+    enum:
+      - adi,adf4382
+      - adi,adf4382a
+
+  reg:
+    maxItems: 1
+
+  spi-max-frequency:
+    maximum: 75000000
+
+  clocks:
+    description: Clock to provide CLKIN reference clock signal.
+    maxItems: 1
+
+  clock-names:
+    description:
+      External clock that provides reference input frequency.
+    items:
+      - const: ref_clk
+
+  '#clock-cells':
+    const: 0
+
+  clock-output-names:
+    maxItems: 1
+
+  adi,charge-pump-microamp:
+    description:
+      The charge pump current that the external loop filter was designed for.
+      If this property is not specified, then the charge pump current is set to the
+      default 11100uA. The valid values are listed below. However, if the set value is
+      not supported, the driver will look for the closest valid charge pump current.
+    anyOf:
+      - enum: [790, 990, 1190, 1380, 1590, 1980, 2390, 2790, 3180, 3970, 4770, 5570, 6330, 7910, 9510, 11100]
+
+  adi,ref-divider:
+    description:
+      Input divider of the reference frequency, cannot be lower then 1 or
+      higher then 63.
+    allOf:
+      - $ref: /schemas/types.yaml#/definitions/uint32
+      - minimum: 1
+      - maximum: 63
+      - default: 1
+    maxItems: 1
+
+  adi,ref-doubler-enable:
+    description:
+      Enables the doubling of the reference clock.
+    type: boolean
+    maxItems: 1
+
+  adi,bleed-word:
+    description:
+      A small programmable constant charge pump current, known as bleed current,
+      can be used to optimize the phase noise and fractional spurious signals
+      in fractional mode.
+    allOf:
+      - $ref: /schemas/types.yaml#/definitions/uint32
+      - minimum: 0
+      - maximum: 4095
+      - default: 0
+    maxItems: 1
+
+  adi,power-up-frequency:
+    description:
+      PLL tunes to the set frequency on probe or defaults to 2,305 GHz.
+    allOf:
+      - $ref: /schemas/types.yaml#/definitions/uint64
+      - minimum: 687500000
+      - maximum: 22000000000
+      - default: 2305000000
+    maxItems: 1
+
+  adi,output-power-value:
+    description:
+      The output power amplitude level which will be applied for both channels
+      at startup.
+    allOf:
+      - $ref: /schemas/types.yaml#/definitions/uint32
+      - minimum: 0
+      - maximum: 15
+      - default: 11
+    maxItems: 1
+
+  adi,spi-3wire-enable:
+    description:
+      Uses SPI in 3 wire mode, by default is uses 4 wire mode.
+    type: boolean
+    maxItems: 1
+
+  adi,cmos-3v3:
+    description:
+      Sets the SPI logic to 3.3V, by defautl it uses 1,8V.
+    type: boolean
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+
+additionalProperties: false
+
+examples:
+  - |
+    spi {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        frequency@0 {
+          compatible = "adi,adf4382";
+          reg = <0>;
+          spi-max-frequency = <1000000>;
+          clocks = <&adf4382_clkin>;
+          clock-names = "ref_clk";
+          adi,charge-pump-current = <15>;
+          adi,ref-divider = <1>;
+        };
+    };
+...
-- 
2.43.0