Re: [PATCH 1/3] clk: ralink: mtmips: fix clock plan for Ralink SoC RT3883

[Stephen Boyd]

Quoting Sergio Paracuellos (2024-09-09 21:40:22)
> Clock plan for Ralink SoC RT3883 needs an extra 'periph' clock to properly
> set some peripherals that has this clock as their parent. When this driver
> was mainlined we could not find any active users of this SoC so we cannot
> perform any real tests for it. Now, one user of a Belkin f9k1109 version 1
> device which uses this SoC appear and reported some issues in openWRT:
> - https://github.com/openwrt/openwrt/issues/16054
> The peripherals that are wrong are 'uart', 'i2c', 'i2s' and 'uartlite' which
> has a not defined 'periph' clock as parent. Hence, introduce it to have a
> properly working clock plan for this SoC.
> 
> Fixes: 6f3b15586eef ("clk: ralink: add clock and reset driver for MTMIPS SoCs")
> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@xxxxxxxxx>
> ---

Applied to clk-next