Re: [PATCH 3/3] clk: ralink: mtmips: add mmc related clocks for SoCs MT7620, MT7628 and MT7688

[Stephen Boyd]

Quoting Sergio Paracuellos (2024-09-09 21:40:24)
> Original architecture clock code from where this driver was derived did not
> include nothing related to mmc clocks. OpenWRT people started to use mtk-sd
> upstream driver recently and they were forced to use a dts 'fixed-clock'
> node with 48 MHz clock:
> - https://github.com/openwrt/openwrt/pull/15896
> The proper thing to do to avoid that is to add the mmc related clocks to the
> driver to avoid a dts with fixed clocks nodes. The minimal documentation in
> the mt7620 programming guide says that there is a BBP_PLL clock of 480 MHz
> derived from the 40 MHz XTAL and from there a clock divider by ten produces
> the desired SDHC clock of 48 MHz for the mmc. Hence add a fixed clock 'bbppll'
> and factor clock 'sdhc' ten divider child to properly set the 'mmc' peripheral
> clock with the desired 48 Mhz rate.
> 
> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@xxxxxxxxx>
> ---

Applied to clk-next