Re: [PATCH v2 05/10] clk: eyeq: add fixed factor clocks infrastructure

From: Stephen Boyd
Date: Thu Nov 14 2024 - 18:00:27 EST


Quoting Théo Lebrun (2024-11-06 08:03:56)
> Driver can currently host two types of clocks:
> - PLLs derived directly from the main crystal (taken using a fwhandle).
> - Divider clocks derived from those PLLs.
>
> PLLs can be instantiated from of_clk_init() or platform device probe,
> using two separate clock providers. Divider clocks are all instantiated
> at platform device probe.
>
> Add a third type of clocks: fixed factors. Those can be instantiated at
> both stages. They can be parented to any clock from the driver. Early
> match data and match data store the list of fixed factor clocks.
>
> Signed-off-by: Théo Lebrun <theo.lebrun@xxxxxxxxxxx>
> ---

Applied to clk-next