Re: [PATCH v2 08/10] clk: eyeq: add EyeQ6H west fixed factor clocks

[Stephen Boyd]

Quoting Théo Lebrun (2024-11-06 08:03:59)
> Previous setup was:
>  - pll-west clock registered from driver at of_clk_init();
>  - Both OCC and UART clocks registered from DT using fixed-factor-clock
>    compatible.
> 
> Now that drivers/clk/clk-eyeq.c supports registering fixed factors, use
> that capability to register west-per-occ and west-per-uart (giving them
> proper names at the same time).
> 
> Also switch from hard-coded index 0 for pll-west to using the
> EQ6HC_WEST_PLL_PER constant by exposed dt-bindings headers.
> 
> All get exposed at of_clk_init() because they get used by the AMBA PL011
> serial ports. Those are instantiated before platform bus infrastructure.
> 
> Signed-off-by: Théo Lebrun <theo.lebrun@xxxxxxxxxxx>
> ---

Applied to clk-next