Re: [PATCH v1 7/7] drm/mediatek: Introduce HDMI/DDC v2 for MT8195/MT8188

[CK Hu (胡俊光)]

Hi, Angelo:

On Wed, 2024-11-20 at 13:45 +0100, AngeloGioacchino Del Regno wrote:
> External email : Please do not click links or open attachments until you have verified the sender or the content.
> 
> 
> Add support for the newer HDMI-TX (Encoder) v2 and DDC v2 IPs
> found in MediaTek's MT8195, MT8188 SoC and their variants, and
> including support for display modes up to 4k60 and for HDMI
> Audio, as per the HDMI 2.0 spec.
> 
> HDCP and CEC functionalities are also supported by this hardware,
> but are not included in this commit.
> 
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxx>
> ---

[snip]

> +static void mtk_hdmi_v2_bridge_pre_enable(struct drm_bridge *bridge,
> +                                         struct drm_bridge_state *old_state)
> +{
> +       struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
> +       struct drm_atomic_state *state = old_state->base.state;
> +       union phy_configure_opts opts = {
> +               .dp = { .link_rate = hdmi->mode.clock * KILO }
> +       };
> +
> +       /* Retrieve the connector through the atomic state */
> +       hdmi->curr_conn = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder);

I would like v1 and v2 has the same behavior. In v1, this is done in bridge enable function.
If it should be here in v2, add comment to describe the reason.

> +       mtk_hdmi_output_set_display_mode(hdmi, &hdmi->mode);

Ditto.

> +
> +       /* Reconfigure phy clock link with appropriate rate */
> +       phy_configure(hdmi->phy, &opts);
> +
> +       /* Power on the PHY here to make sure that DPI_HDMI is clocked */
> +       phy_power_on(hdmi->phy);

Ditto.

> +
> +       /* Enable VSync interrupt */
> +       regmap_set_bits(hdmi->regs, TOP_INT_ENABLE00, HDMI_VSYNC_INT);

I do not see software do anything in vsync.
I think this is not necessary, so drop it.

Regards,
CK

> +
> +       hdmi->powered = true;
> +}
> +