Re: [PATCH 8/9] arm64: dts: renesas: r8a779h0: Add display support

[Tomi Valkeinen]

Hi,

On 03/12/2024 11:37, Laurent Pinchart wrote:
> Hi Tomi,
>
> Thank you for the patch.
>
> On Tue, Dec 03, 2024 at 10:01:42AM +0200, Tomi Valkeinen wrote:
> > From: Tomi Valkeinen <tomi.valkeinen+renesas@xxxxxxxxxxxxxxxx>
> >
> > Add the device nodes for supporting DU and DSI.
> >
> > Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@xxxxxxxxxxxxxxxx>
> > ---
> >   arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 77 +++++++++++++++++++++++++++++++
> >   1 file changed, 77 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi
> > index 12d8be3fd579..82df6ee98afb 100644
> > --- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi
> > @@ -1828,6 +1828,54 @@ csi41isp1: endpoint {
> >   			};
> >   		};
> >   
> > +		fcpvd0: fcp@fea10000 {
> > +			compatible = "renesas,fcpv";
> > +			reg = <0 0xfea10000 0 0x200>;
> > +			clocks = <&cpg CPG_MOD 508>;
> > +			power-domains = <&sysc R8A779H0_PD_C4>;
> > +			resets = <&cpg 508>;
> > +		};
> > +
> > +		vspd0: vsp@fea20000 {
> > +			compatible = "renesas,vsp2";
> > +			reg = <0 0xfea20000 0 0x8000>;
> > +			interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>;
>
> The documentation lists this interrupt as being LevelSensitive and
> Negative. I wouldn't expect the VSP to work at all with a wrong polarity
> in DT, so the level may get inverted somewhere.

Indeed... It's the same for V4H. And it also has IRQ_TYPE_LEVEL_HIGH in 
the dts. I tried changing it to LOW on V4H, but:

genirq: Setting trigger mode 8 for irq 91 failed
vsp1 fea20000.vsp: failed to request IRQ

I didn't dig further yet.

> > +			clocks = <&cpg CPG_MOD 830>;
> > +			power-domains = <&sysc R8A779H0_PD_C4>;
> > +			resets = <&cpg 830>;
> > +			renesas,fcp = <&fcpvd0>;
> > +		};
> > +
> > +		du: display@feb00000 {
> > +			compatible = "renesas,du-r8a779h0";
> > +			reg = <0 0xfeb00000 0 0x40000>;
> > +			interrupts = <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>;
> > +			clocks = <&cpg CPG_MOD 411>;
> > +			clock-names = "du.0";
> > +			power-domains = <&sysc R8A779H0_PD_C4>;
> > +			resets = <&cpg 411>;
> > +			reset-names = "du.0";
> > +			renesas,vsps = <&vspd0 0>;
> > +
> > +			status = "disabled";
> > +
> > +			ports {
> > +				#address-cells = <1>;
> > +				#size-cells = <0>;
> > +
> > +				port@0 {
> > +					reg = <0>;
> > +					du_out_dsi0: endpoint {
> > +						remote-endpoint = <&dsi0_in>;
> > +					};
> > +				};
> > +
> > +				port@1 {
> > +					reg = <1>;
> > +				};
>
> On V4M the DU has a single channel, so there should be a single port.

Yep, I'll drop.

 Tomi

> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@xxxxxxxxxxxxxxxx>
>
> > +			};
> > +		};
> > +
> >   		isp0: isp@fed00000 {
> >   			compatible = "renesas,r8a779h0-isp",
> >   				     "renesas,rcar-gen4-isp";
> > @@ -1996,6 +2044,35 @@ isp1vin15: endpoint {
> >   			};
> >   		};
> >   
> > +		dsi0: dsi-encoder@fed80000 {
> > +			compatible = "renesas,r8a779h0-dsi-csi2-tx";
> > +			reg = <0 0xfed80000 0 0x10000>;
> > +			clocks = <&cpg CPG_MOD 415>,
> > +				 <&cpg CPG_CORE R8A779H0_CLK_DSIEXT>,
> > +				 <&cpg CPG_CORE R8A779H0_CLK_DSIREF>;
> > +			clock-names = "fck", "dsi", "pll";
> > +			power-domains = <&sysc R8A779H0_PD_C4>;
> > +			resets = <&cpg 415>;
> > +
> > +			status = "disabled";
> > +
> > +			ports {
> > +				#address-cells = <1>;
> > +				#size-cells = <0>;
> > +
> > +				port@0 {
> > +					reg = <0>;
> > +					dsi0_in: endpoint {
> > +						remote-endpoint = <&du_out_dsi0>;
> > +					};
> > +				};
> > +
> > +				port@1 {
> > +					reg = <1>;
> > +				};
> > +			};
> > +		};
> > +
> >   		prr: chipid@fff00044 {
> >   			compatible = "renesas,prr";
> >   			reg = <0 0xfff00044 0 4>;