Re: [RFC PATCH v2 00/21] riscv: Introduce 64K base page

[David Hildenbrand]

On 06.12.24 03:00, Zi Yan wrote:
> On 5 Dec 2024, at 5:37, Xu Lu wrote:
>
> > This patch series attempts to break through the limitation of MMU and
> > supports larger base page on RISC-V, which only supports 4K page size
> > now. The key idea is to always manage and allocate memory at a
> > granularity of 64K and use SVNAPOT to accelerate address translation.
> > This is the second version and the detailed introduction can be found
> > in [1].
> >
> > Changes from v1:
> > - Rebase on v6.12.
> >
> > - Adjust the page table entry shift to reduce page table memory usage.
> >      For example, in SV39, the traditional va behaves as:
> >
> >      ----------------------------------------------
> >      | pgd index | pmd index | pte index | offset |
> >      ----------------------------------------------
> >      | 38     30 | 29     21 | 20     12 | 11   0 |
> >      ----------------------------------------------
> >
> >      When we choose 64K as basic software page, va now behaves as:
> >
> >      ----------------------------------------------
> >      | pgd index | pmd index | pte index | offset |
> >      ----------------------------------------------
> >      | 38     34 | 33     25 | 24     16 | 15   0 |
> >      ----------------------------------------------
> >
> > - Fix some bugs in v1.
> >
> > Thanks in advance for comments.
> >
> > [1] https://lwn.net/Articles/952722/
>
> This looks very interesting. Can you cc me and linux-mm@xxxxxxxxx
> in the future? Thanks.
>
> Have you thought about doing it for ARM64 4KB as well? ARM64’s contig PTE
> should have similar effect of RISC-V’s SVNAPOT, right?

What is the real benefit over 4k + large folios/mTHP?

64K comes with the problem of internal fragmentation: for example, a 
page table that only occupies 4k of memory suddenly consumes 64K; quite 
a downside.

--
Cheers,

David / dhildenb