RE: [PATCH v6 RESEND net-next 2/5] net: enetc: add Tx checksum offload for i.MX95 ENETC

[Wei Fang]

> -----Original Message-----
> From: Simon Horman <horms@xxxxxxxxxx>
> Sent: 2024年12月6日 17:37
> To: Wei Fang <wei.fang@xxxxxxx>
> Cc: Claudiu Manoil <claudiu.manoil@xxxxxxx>; Vladimir Oltean
> <vladimir.oltean@xxxxxxx>; Clark Wang <xiaoning.wang@xxxxxxx>;
> andrew+netdev@xxxxxxx; davem@xxxxxxxxxxxxx; edumazet@xxxxxxxxxx;
> kuba@xxxxxxxxxx; pabeni@xxxxxxxxxx; Frank Li <frank.li@xxxxxxx>;
> netdev@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; imx@xxxxxxxxxxxxxxx
> Subject: Re: [PATCH v6 RESEND net-next 2/5] net: enetc: add Tx checksum
> offload for i.MX95 ENETC
> 
> On Wed, Dec 04, 2024 at 01:29:29PM +0800, Wei Fang wrote:
> > In addition to supporting Rx checksum offload, i.MX95 ENETC also supports
> > Tx checksum offload. The transmit checksum offload is implemented through
> > the Tx BD. To support Tx checksum offload, software needs to fill some
> > auxiliary information in Tx BD, such as IP version, IP header offset and
> > size, whether L4 is UDP or TCP, etc.
> >
> > Same as Rx checksum offload, Tx checksum offload capability isn't defined
> > in register, so tx_csum bit is added to struct enetc_drvdata to indicate
> > whether the device supports Tx checksum offload.
> >
> > Signed-off-by: Wei Fang <wei.fang@xxxxxxx>
> > Reviewed-by: Frank Li <Frank.Li@xxxxxxx>
> > Reviewed-by: Claudiu Manoil <claudiu.manoil@xxxxxxx>
> 
> ...
> 
> > diff --git a/drivers/net/ethernet/freescale/enetc/enetc_hw.h
> b/drivers/net/ethernet/freescale/enetc/enetc_hw.h
> > index 4b8fd1879005..590b1412fadf 100644
> > --- a/drivers/net/ethernet/freescale/enetc/enetc_hw.h
> > +++ b/drivers/net/ethernet/freescale/enetc/enetc_hw.h
> > @@ -558,7 +558,12 @@ union enetc_tx_bd {
> >  		__le16 frm_len;
> >  		union {
> >  			struct {
> > -				u8 reserved[3];
> > +				u8 l3_start:7;
> > +				u8 ipcs:1;
> > +				u8 l3_hdr_size:7;
> > +				u8 l3t:1;
> > +				u8 resv:5;
> > +				u8 l4t:3;
> >  				u8 flags;
> >  			}; /* default layout */
> 
> Hi Wei,
> 
> Given that little-endian types are used elsewhere in this structure
> I am guessing that the layout above works for little-endian hosts
> but will not work on big-endian hosts.
> 
> If so, I would suggest an alternate approach of using a single 32-bit
> word and accessing it using a combination of FIELD_PREP() and FIELD_GET()
> using masks created using GENMASK() and BIT().

Good suggestion, I will refine it, thanks.

> 
> Or, less desirably IMHO, by providing an alternate layout for
> the embedded struct for big endian systems.
> 
> ...