Re: [PATCH v3 1/2] Introduce cpu_icache_is_aliasing() across all architectures

[Mathieu Desnoyers]

On 2024-12-07 12:01, Mathieu Desnoyers wrote:
> On 2024-12-07 11:55, Zi Yan wrote:
> > In commit eacd0e950dc2 ("ARC: [mm] Lazy D-cache flush (non aliasing
> > VIPT)"), arc adds the need to flush dcache to make icache see the code
> > page change. This also requires special handling for
> > clear_user_(high)page(). Introduce cpu_icache_is_aliasing() to make
> > MM code query special clear_user_(high)page() easier. This will be used
> > by the following commit.
> >
> > Suggested-by: Mathieu Desnoyers <mathieu.desnoyers@xxxxxxxxxxxx>
> > Signed-off-by: Zi Yan <ziy@xxxxxxxxxx>
>
> Reviewed-by: Mathieu Desnoyers <mathieu.desnoyers@xxxxxxxxxxxx>
We should probably use this new cpu_icache_is_aliasing() to gate
availability of DAX XIP, as described in the commit message here:

commit 8690bbcf3b ("Introduce cpu_dcache_is_aliasing() across all architectures)"

    Note that this leaves "cpu_icache_is_aliasing()" to be implemented as future
    work. This would be useful to gate features like XIP on architectures
    which have aliasing CPU dcache-icache but not CPU dcache-dcache.

Thanks,

Mathieu

> > ---
> >   arch/arc/Kconfig                 | 1 +
> >   arch/arc/include/asm/cachetype.h | 8 ++++++++
> >   include/linux/cacheinfo.h        | 6 ++++++
> >   3 files changed, 15 insertions(+)
> >   create mode 100644 arch/arc/include/asm/cachetype.h
> >
> > diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
> > index 5b2488142041..e96935373796 100644
> > --- a/arch/arc/Kconfig
> > +++ b/arch/arc/Kconfig
> > @@ -6,6 +6,7 @@
> >   config ARC
> >       def_bool y
> >       select ARC_TIMERS
> > +    select ARCH_HAS_CPU_CACHE_ALIASING
> >       select ARCH_HAS_CACHE_LINE_SIZE
> >       select ARCH_HAS_DEBUG_VM_PGTABLE
> >       select ARCH_HAS_DMA_PREP_COHERENT
> > diff --git a/arch/arc/include/asm/cachetype.h 
> > b/arch/arc/include/asm/cachetype.h
> > new file mode 100644
> > index 000000000000..acd3b6cb4bf5
> > --- /dev/null
> > +++ b/arch/arc/include/asm/cachetype.h
> > @@ -0,0 +1,8 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +#ifndef __ASM_ARC_CACHETYPE_H
> > +#define __ASM_ARC_CACHETYPE_H
> > +
> > +#define cpu_dcache_is_aliasing()    false
> > +#define cpu_icache_is_aliasing()    true
> > +
> > +#endif
> > diff --git a/include/linux/cacheinfo.h b/include/linux/cacheinfo.h
> > index 108060612bb8..7ad736538649 100644
> > --- a/include/linux/cacheinfo.h
> > +++ b/include/linux/cacheinfo.h
> > @@ -155,8 +155,14 @@ static inline int get_cpu_cacheinfo_id(int cpu, 
> > int level)
> >   #ifndef CONFIG_ARCH_HAS_CPU_CACHE_ALIASING
> >   #define cpu_dcache_is_aliasing()    false
> > +#define cpu_icache_is_aliasing()    cpu_dcache_is_aliasing()
> >   #else
> >   #include <asm/cachetype.h>
> > +
> > +#ifndef cpu_icache_is_aliasing
> > +#define cpu_icache_is_aliasing()    cpu_dcache_is_aliasing()
> > +#endif
> > +
> >   #endif
> >   #endif /* _LINUX_CACHEINFO_H */

--
Mathieu Desnoyers
EfficiOS Inc.
https://www.efficios.com