Add devicetree binding for mediatek common-dramc driver.
The DRAM controller of MediaTek SoC provides an interface to
get the current data rate of DRAM.
Signed-off-by: Crystal Guo <crystal.guo@xxxxxxxxxxxx>
---
.../mediatek,common-dramc.yaml | 129 ++++++++++++++++++
1 file changed, 129 insertions(+)
create mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,common-dramc.yaml
diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,common-dramc.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,common-dramc.yaml
new file mode 100644
index 000000000000..c9e608c7f183
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,common-dramc.yaml
@@ -0,0 +1,129 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+# Copyright (c) 2024 MediaTek Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/memory-controllers/mediatek,common-dramc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Common DRAMC (DRAM Controller)
+
+maintainers:
+ - Crystal Guo <crystal.guo@xxxxxxxxxxxx>
+
+description: |
+ The DRAM controller of MediaTek SoC provides an interface to
+ get the current data rate of DRAM.
+
+properties:
+ compatible:
+ const: mediatek,common-dramc
+
+ reg:
+ minItems: 9
+ items:
+ - description: DRAMC_AO_CHA_BASE
+ - description: DRAMC_AO_CHB_BASE
+ - description: DRAMC_AO_CHC_BASE
+ - description: DRAMC_AO_CHD_BASE
+ - description: DRAMC_NAO_CHA_BASE
+ - description: DRAMC_NAO_CHB_BASE
+ - description: DRAMC_NAO_CHC_BASE
+ - description: DRAMC_NAO_CHD_BASE
+ - description: DDRPHY_AO_CHA_BASE
+ - description: DDRPHY_AO_CHB_BASE
+ - description: DDRPHY_AO_CHC_BASE
+ - description: DDRPHY_AO_CHD_BASE
+ - description: DDRPHY_NAO_CHA_BASE
+ - description: DDRPHY_NAO_CHB_BASE
+ - description: DDRPHY_NAO_CHC_BASE
+ - description: DDRPHY_NAO_CHD_BASE
+ - description: SLEEP_BASE
+
+ support-ch-cnt:
+ maxItems: 1
+
+ fmeter-version:
+ maxItems: 1
+ description:
+ Fmeter version for calculating dram data rate
+
+ crystal-freq:
+ maxItems: 1
+ description:
+ Reference clock rate in MHz
+
+ shu-of:
+ maxItems: 1
+
+ pll-id: true
+ shu-lv: true
+ sdmpcw: true
+ posdiv: true
+ fbksel: true
+ dqsopen: true
+ async-ca: true
+ dq-ser-mode: true