Re: [PATCH v7 2/2] rust: add dma coherent allocator abstraction.

[Robin Murphy]

On 13/12/2024 2:47 pm, Daniel Almeida wrote:
[...]
> > > +    /// Returns the CPU-addressable region as a slice.
> > > +    pub fn cpu_buf(&self) -> &[T]
> > > +    {
> > > +        // SAFETY: The pointer is valid due to type invariant on `CoherentAllocation` and
> > > +        // is valid for reads for `self.count * size_of::<T>` bytes.
> > > +        unsafe { core::slice::from_raw_parts(self.cpu_addr, self.count) }
> >
> > Immutable slices require that the data does not change while the
> > reference is live. Is that the case? If so, your safety comment should
> > explain that.
> >
> > > +    }
> > > +
> > > +    /// Performs the same functionality as `cpu_buf`, except that a mutable slice is returned.
> > > +    pub fn cpu_buf_mut(&mut self) -> &mut [T]
> > > +    {
> > > +        // SAFETY: The pointer is valid due to type invariant on `CoherentAllocation` and
> > > +        // is valid for reads for `self.count * size_of::<T>` bytes.
> > > +        unsafe { core::slice::from_raw_parts_mut(self.cpu_addr, self.count) }
> >
> > Mutable slices require that the data is not written to *or read* by
> > anybody else while the reference is live. Is that the case? If so,
> > your safety comment should explain that.
>
> The buffer will probably be shared between the CPU and some hardware device, since this is the
> point of the dma mapping API.
>
> It’s up to the caller to ensure that no hardware operations that involve the buffer are currently taking
> place while the slices above are alive.

Hmm, that sounds troublesome... the nature of coherent allocations is 
that both CPU and device may access them at any time, and you can 
definitely expect ringbuffer-style usage models where a CPU is writing 
to part of the buffer while the device is reading/writing another part, 
but also cases where a CPU needs to poll for a device write to a 
particular location.

Thanks,
Robin.

> I think that adding that as a safety requirement to `cpu_buf` and `cpu_buf_mut` will be sufficient.
>
> > > +    }
> > > +}
> > > +
> > > +impl<T: AsBytes + FromBytes> Drop for CoherentAllocation<T> {
> > > +    fn drop(&mut self) {
> > > +        let size = self.count * core::mem::size_of::<T>();
> > > +        // SAFETY: the device, cpu address, and the dma handle is valid due to the
> > > +        // type invariants on `CoherentAllocation`.
> > > +        unsafe { bindings::dma_free_attrs(self.dev.as_raw(), size,
> > > +                                          self.cpu_addr as _,
> > > +                                          self.dma_handle,
> > > +                                          self.dma_attrs.as_raw(),) }
> > > +    }
> > > +}
> > > diff --git a/rust/kernel/lib.rs b/rust/kernel/lib.rs
> > > index e1065a7551a3..6e90ebf5a130 100644
> > > --- a/rust/kernel/lib.rs
> > > +++ b/rust/kernel/lib.rs
> > > @@ -35,6 +35,7 @@
> > > mod build_assert;
> > > pub mod cred;
> > > pub mod device;
> > > +pub mod dma;
> > > pub mod error;
> > > #[cfg(CONFIG_RUST_FW_LOADER_ABSTRACTIONS)]
> > > pub mod firmware;
> > > —
> > > 2.43.0
>
> — Daniel