Re: [PATCH V2 18/46] arm64/sysreg: Add register fields for PMUACR_EL1

[Rob Herring]

On Tue, Dec 10, 2024 at 11:22:43AM +0530, Anshuman Khandual wrote:
> This adds register fields for PMUACR_EL1 as per the definitions based
> on DDI0601 2024-09.
> 
> Cc: Catalin Marinas <catalin.marinas@xxxxxxx>
> Cc: Will Deacon <will@xxxxxxxxxx>
> Cc: Mark Brown <broonie@xxxxxxxxxx>
> Cc: linux-arm-kernel@xxxxxxxxxxxxxxxxxxx
> Cc: linux-kernel@xxxxxxxxxxxxxxx
> Signed-off-by: Anshuman Khandual <anshuman.khandual@xxxxxxx>
> ---
>  arch/arm64/tools/sysreg | 37 +++++++++++++++++++++++++++++++++++++
>  1 file changed, 37 insertions(+)
> 
> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> index 214ad6da1dff..462adb8031ca 100644
> --- a/arch/arm64/tools/sysreg
> +++ b/arch/arm64/tools/sysreg
> @@ -2349,6 +2349,43 @@ Res0	63:5
>  Field	4:0	SEL
>  EndSysreg
>  
> +Sysreg	PMUACR_EL1	3	0	9	14	4

I already added this and various other PMUv3.9 registers you've added 
here in v6.12 and v6.13. So are you on an old base or the tool allows 
multiple definitions? If the latter, that should be fixed.

> +Res0	63:33
> +Field	32	FM
> +Field	31	C
> +Field	30	P30
> +Field	29	P29
> +Field	28	P28
> +Field	27	P27
> +Field	26	P26
> +Field	25	P25
> +Field	24	P24
> +Field	23	P23
> +Field	22	P22
> +Field	21	P21
> +Field	20	P20
> +Field	19	P19
> +Field	18	P18
> +Field	17	P17
> +Field	16	P16
> +Field	15	P15
> +Field	14	P14
> +Field	13	P13
> +Field	12	P12
> +Field	11	P11
> +Field	10	P10
> +Field	9	P9
> +Field	8	P8
> +Field	7	P7
> +Field	6	P6
> +Field	5	P5
> +Field	4	P4
> +Field	3	P3
> +Field	2	P2
> +Field	1	P1
> +Field	0	P0

We're never going to use Pnn defines. This is just useless bloat unless 
we're aiming to top amd gpu defines LOC.

Rob