Re: [PATCH 09/10] x86/mm: enable AMD translation cache extensions

[Peter Zijlstra]

On Sat, Dec 21, 2024 at 11:06:41PM -0500, Rik van Riel wrote:
> With AMD TCE (translation cache extensions) only the intermediate mappings

Only the leave mapings, as written this all don't make sense,

> that cover the address range zapped by INVLPG / INVLPGB get invalidated,
> rather than all intermediate mappings getting zapped at every TLB invalidation.
> 
> This can help reduce the TLB miss rate, by keeping more intermediate
> mappings in the cache.