Re: [PATCH v4] drm: bridge: fsl-ldb: fixup mode on freq mismatch

[Miquel Raynal]

Hello Martin,

On 19/12/2024 at 12:39:05 GMT, Martin Kepplinger <martink@xxxxxxxxx> wrote:

> Am Donnerstag, dem 19.12.2024 um 11:54 +0100 schrieb Nikolaus Voss:
>> LDB clock has to be a fixed multiple of the pixel clock.
>> Although LDB and pixel clock have a common source, this
>> constraint cannot be satisfied for any pixel clock at a
>> fixed source clock.
>> 
>> Violating this constraint leads to flickering and distorted
>> lines on the attached display.
>> 
>> To overcome this, there are these approches:
>> 
>> 1. Modify the base PLL clock statically by changing the
>>    device tree, implies calculating the PLL clock by
>>    hand, e.g. commit 4fbb73416b10 ("arm64: dts:
>>    imx8mp-phyboard-pollux: Set Video PLL1 frequency to 506.8 MHz")
>> 
>> 2. Walk down the clock tree and modify the source clock.
>>    Proposed patch series by Miquel Raynal:
>>    [PATCH 0/5] clk: Fix simple video pipelines on i.MX8
>> 
>> 3. This patch: check constraint violation in
>>    drm_bridge_funcs.atomic_check() and adapt the pixel
>>    clock in drm_display_mode.adjusted_mode accordingly.
>> 
>> Fixes: 463db5c2ed4a ("drm: bridge: ldb: Implement simple Freescale
>> i.MX8MP LDB bridge")
>> Cc: <stable@xxxxxxxxxxxxxxx> # 6.12.x, 6.6.x
>> Signed-off-by: Nikolaus Voss <nv@xxxxxxx>
>> 
>> ---

I didn't investigate further, but FYI this approach does not fix my
situation with iMX8MP. I am not saying it's wrong, because I am not
experienced enough with drm, but at least that it is not a replacement
of point #2 above.

Cheers,
Miquèl